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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21354/DS213554 single-chip transceivers (SCTs) contain all the necessary functions to connect to E1 lines. The devices are upward-compatible versions of the DS2153 and DS2154 SCTs. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. Both devices automatically adjust to E1 22AWG (0.6mm) twistedpair cables from 0 to over 2km in length. They can generate the necessary G.703 waveshapes for both 75W coax and 120W twisted cables. The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information. The on-board HDLC controller can be used for Sa-bit links or DS0s. The devices contain a set of internal registers that the user can access to control the operation of the units. Quick access through the parallel control port allows a single controller to handle many E1 lines. The devices fully meet all the latest E1 specifications, including ITU-T G.703, G.704, G.706, G.823, G.732, and I.431, ETS 300 011, 300 233, and 300 166, as well as CTR12 and CTR4.

FEATURES
Complete E1 (CEPT) PCM-30/ISDN-PRI Transceiver Functionality On-Board Long- and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Frames to FAS, CAS, CCS, and CRC4 Formats Integral HDLC Controller with 64-Byte Buffers Configurable for Sa Bits, DS0, or Sub-DS0 Operation Dual Two-Frame Elastic Store Slip Buffers that can Connect to Asynchronous Backplanes up to 8.192MHz Interleaving PCM Bus Operation 8-Bit Parallel Control Port that can be used Directly on Either Multiplexed or Nonmultiplexed Buses (Intel or Motorola) Extracts and Inserts CAS Signaling Detects and Generates Remote and AIS Alarms Programmable Output Clocks for Fractional E1, H0, and H12 Applications Fully Independent Transmit and Receive Functionality Full Access to Si and Sa Bits Aligned with CRC-4 Multiframe Four Separate Loopback Functions for Testing Functions Large Counters for Bipolar and Code Violations, CRC4 Codeword Errors, FAS Word Errors, and E Bits IEEE 1149.1 JTAG-Boundary Scan Architecture Pin Compatible with DS2154/52/352/552 SCTs 3.3V (DS21354) or 5V (DS21554) Supply; LowPower CMOS 100-pin LQFP package (14mm x 14mm)
PART DS21354L TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PIN-PACKAGE 100 LQFP 100 LQFP 100 LQFP 100 LQFP
PIN CONFIGURATION
TOP VIEW
Dallas Semiconductor DS21354/DS21554

ORDERING INFORMATION
100 1
DS21354LN
LQFP
DS21554L DS21554LN
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 021004
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
TABLE OF CONTENTS
1. INTRODUCTION.................................................................................................................. 6
1.1. FUNCTIONAL DESCRIPTION..............................................................................................................................7 1.2. DOCUMENT REVISION HISTORY .............................................................................................................8
2. BLOCK DIAGRAM .............................................................................................................. 9 3. PIN DESCRIPTION............................................................................................................ 10
3.1. PIN FUNCTION DESCRIPTION ................................................................................................................14 3.1.1. Transmit-Side Pins..............................................................................................................................14 3.1.2. Receive-Side Pins...............................................................................................................................17 3.1.3. Parallel Control Port Pins ....................................................................................................................20 3.1.4. JTAG Test Access Port Pins...............................................................................................................22 3.1.5. Interleave Bus Operation Pins ............................................................................................................22 3.1.6. Line Interface Pins ..............................................................................................................................23 3.1.7. Supply Pins .........................................................................................................................................24
4. PARALLEL PORT ............................................................................................................. 25
4.1. REGISTER MAP ........................................................................................................................................25
5. CONTROL, ID, AND TEST REGISTERS .......................................................................... 30
5.1. 5.2. 5.3. 5.4. 5.5. 5.6. POWER-UP SEQUENCE ..........................................................................................................................30 SYNCHRONIZATION AND RESYNCHRONIZATION...............................................................................32 FRAMER LOOPBACK ...............................................................................................................................36 AUTOMATIC ALARM GENERATION........................................................................................................38 REMOTE LOOPBACK ...............................................................................................................................40 LOCAL LOOPBACK...................................................................................................................................40
6. STATUS AND INFORMATION REGISTERS .................................................................... 43
6.1. CRC4 SYNC COUNTER............................................................................................................................45
7. ERROR COUNT REGISTERS........................................................................................... 50
7.1. 7.2. 7.3. 7.4. BPV OR CODE VIOLATION COUNTER ...................................................................................................50 CRC4 ERROR COUNTER.........................................................................................................................51 E-BIT COUNTER .......................................................................................................................................51 FAS ERROR COUNTER .................................................................................................................................52
8. DS0 MONITORING FUNCTION ........................................................................................ 53 9. SIGNALING OPERATION................................................................................................. 56
9.1. PROCESSOR-BASED SIGNALING ..........................................................................................................56 9.2. HARDWARE-BASED SIGNALING ............................................................................................................58 9.2.1. Receive Side .......................................................................................................................................58 9.2.2. Transmit Side ......................................................................................................................................59
10. PER-CHANNEL CODE GENERATION AND LOOPBACK............................................... 60
10.1. TRANSMIT-SIDE CODE GENERATION ................................................................................................60 10.1.1. Simple Idle Code Insertion and Per-Channel Loopback.....................................................................60 10.1.2. Per-Channel Code Insertion ...............................................................................................................61 10.2. RECEIVE-SIDE CODE GENERATION...................................................................................................62
11. CLOCK BLOCKING REGISTERS..................................................................................... 63
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12. ELASTIC STORES OPERATION...................................................................................... 65
12.1. RECEIVE SIDE .......................................................................................................................................65 12.2. TRANSMIT SIDE.....................................................................................................................................65
13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................. 66
13.1. HARDWARE SCHEME ...........................................................................................................................66 13.2. INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME .........................................................66 13.3. INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME....................................................68
14. HDLC CONTROLLER FOR THE SA BITS OR DS0 ......................................................... 70
14.1. GENERAL OVERVIEW ...........................................................................................................................70 14.2. HDLC STATUS REGISTERS..................................................................................................................71 14.3. BASIC OPERATION DETAILS ...............................................................................................................72 14.3.1. Example: Receive an HDLC Message................................................................................................72 14.3.2. Example: Transmit an HDLC Message...............................................................................................72 14.4. HDLC REGISTER DESCRIPTION..........................................................................................................73
15. LINE INTERFACE FUNCTIONS........................................................................................ 80
15.1. 15.2. 15.3. 15.4. 15.5. RECEIVE CLOCK AND DATA RECOVERY.......................................................................................................81 TRANSMIT WAVESHAPING AND LINE DRIVING ..............................................................................................81 JITTER ATTENUATOR..................................................................................................................................82 PROTECTED INTERFACES ...........................................................................................................................86 RECEIVE MONITOR MODE ..........................................................................................................................89
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................... 90
16.1. INSTRUCTION REGISTER.............................................................................................................................95 16.2. TEST REGISTERS.......................................................................................................................................96
17. INTERLEAVED PCM BUS OPERATION .......................................................................... 98
17.1. CHANNEL INTERLEAVE ...............................................................................................................................99 17.2. FRAME INTERLEAVE ...................................................................................................................................99
18. FUNCTIONAL TIMING DIAGRAMS................................................................................ 100
18.1. RECEIVE .................................................................................................................................................100 18.2. TRANSMIT ...............................................................................................................................................104
19. OPERATING PARAMETERS.......................................................................................... 111 20. AC TIMING PARAMETERS AND DIAGRAMS ............................................................... 112
20.1. 20.2. 20.3. 20.4. MULTIPLEXED BUS AC CHARACTERISTICS ................................................................................................112 NONMULTIPLEXED BUS AC CHARACTERISTICS..........................................................................................115 RECEIVE-SIDE AC CHARACTERISTICS ......................................................................................................117 TRANSMIT AC CHARACTERISTICS.............................................................................................................121
21. PACKAGE INFORMATION............................................................................................. 124
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LIST OF FIGURES
Figure 2-1. DS21354/554 Block Diagram ............................................................................................................................. 9 Figure 15-1. Basic External Analog Connections .............................................................................................................. 83 Figure 15-2. Optional Crystal Connection........................................................................................................................... 83 Figure 15-3. Jitter Tolerance................................................................................................................................................. 84 Figure 15-4. Jitter Attenuation .............................................................................................................................................. 84 Figure 15-5. Transmit Waveform Template ........................................................................................................................ 85 Figure 15-6. Protected Interface Example for the DS21554 ............................................................................................ 87 Figure 15-7. Protected Interface Example for the DS21354 ............................................................................................ 88 Figure 15-8. Typical Monitor Port Application .................................................................................................................... 89 Figure 16-1. JTAG Functional Block Diagram.................................................................................................................... 91 Figure 16-2. TAP Controller State Diagram........................................................................................................................ 94 Figure 17-1. IBO Basic Configuration Using Four SCTs .................................................................................................. 99 Figure 18-1. Receive-Side Timing...................................................................................................................................... 100 Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled)................................................................. 100 Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) .............................................. 101 Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) .............................................. 101 Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode ................................................................................ 102 Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode............................................................................. 103 Figure 18-7. Transmit-Side Timing .................................................................................................................................... 104 Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)................................................................ 104 Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ............................................. 105 Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ........................................... 105 Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode ............................................................................. 106 Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode.......................................................................... 107 Figure 18-13. G.802 Timing ................................................................................................................................................ 108 Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart ........................................................................ 109 Figure 18-15. DS21354/DS21554 Transmit Data Flow .................................................................................................. 110 Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1)........................................................................................... 113 Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1)................................................................................................. 113 Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1) ............................................................................................ 114 Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0).......................................................................................... 115 Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0) .......................................................................................... 116 Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0).................................................................................. 116 Figure 20-7. Motorola Bus Write AC Timing (BTS = 1/MUX = 0) .................................................................................. 116 Figure 20-8. Receive-Side AC Timing ............................................................................................................................... 118 Figure 20-9. Receive System Side AC Timing................................................................................................................. 119 Figure 20-10. Receive Line Interface AC Timing............................................................................................................. 120 Figure 20-11. Transmit-Side AC Timing............................................................................................................................ 122 Figure 20-12. Transmit System Side AC Timing.............................................................................................................. 123 Figure 20-13. Transmit Line Interface Side AC Timing................................................................................................... 123
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LIST OF TABLES
Table 3-1. Pin Description Sorted by Pin Number............................................................................................................. 10 Table 3-2. Pin Description by Symbol ................................................................................................................................. 12 Table 4-1. Register Map Sorted by Address ...................................................................................................................... 25 Table 5-1. Device ID Bit Map ................................................................................................................................................ 30 Table 5-2. SYNC/RESYNC Criteria ..................................................................................................................................... 32 Table 6-1. Alarm Criteria ....................................................................................................................................................... 46 Table 14-1. HDLC Controller Register List ......................................................................................................................... 70 Table 15-1. Line Build-Out Select in LICR for the DS21554 ............................................................................................ 81 Table 15-2. Line Build-Out Select in LICR for the DS21354 ............................................................................................ 82 Table 15-3. Transformer Specifications .............................................................................................................................. 82 Table 15-4. Receive Monitor Mode Gain ............................................................................................................................ 89 Table 16-1. Instruction Codes for IEEE 1149.1 Architecture ........................................................................................... 95 Table 16-2. ID Code Structure.............................................................................................................................................. 96 Table 16-3. Device ID Codes................................................................................................................................................ 96 Table 16-4. Boundary Scan Control Bits............................................................................................................................. 97 Table 17-1. IBO Master Device Select ................................................................................................................................ 98
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1. INTRODUCTION
The DS21354/DS21554 are superset versions of the popular DS2153 and DS2154 SCTs offering the new features listed below. All the original features of the DS2153 and DS2154 have been retained, and the software created for the original devices is transferable into the DS21354/DS21554.
New Features in the DS21354 and DS21554
FEATURE HDLC controller with 64-Byte Buffers for Sa Bits or DS0s or Sub DS0s Interleaving PCM Bus Operation IEEE 1149.1 JTAG-Boundary Scan Architecture 3.3V (DS21354 Only) Supply Line Interface Support for the G.703 2.048 Synchronization Interface Customer Disconnect Indication (...101010...) Generator Open-Drain Line Driver Option SECTION 14 17 16 1.1 and 2 15 5.6 5.6
Additional Features in the DS21354 and DS21554
FEATURE Option for nonmultiplexed bus operation Crystal-less jitter attenuation Additional hardware signaling capability including: Receive signaling reinsertion to a backplane multiframe sync Availability of signaling in a separate PCM data stream Signaling freezing Interrupt generated on change of signaling data Improved receive sensitivity: 0 to -43dB Per-channel code insertion in both transmit and receive paths Expanded access to Sa and Si bits RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state 8.192MHz clock synthesizer Per-channel loopback Addition of hardware pins to indicate carrier loss and signaling freeze Line interface function can be completely decoupled from the framer/formatter to allow: Interface to optical, HDSL, and other NRZ interfaces "tap" the transmit and receive bipolar data streams for monitoring purposes Be able to corrupt data and insert framing errors, CRC errors, etc. Transmit and receive elastic stores now have independent backplane clocks Ability to monitor one DS0 channel in both the transmit and receive paths Access to the data streams in between the framer/formatter and the elastic stores AIS generation in the line interface that is independent of loopbacks Transmit current limiter to meet the 50mA short circuit requirement Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Automatic RAI generation to ETS 300 011 specifications SECTION 1.1 and 20.2 15.3 9 1.1 10 13 6 1.1 10 1.1 1.1 1.1 8 1.1 1.1 and 5 15 5.4 5.4
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1.1. Functional Description The analog AMI/HDB3 waveform off the E1 line is transformer coupled into the RRING and RTIP pins of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive-side framer where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS21354/DS21554 contain an active filter that reconstructs the analogreceived signal for the nonlinear losses that occur in transmission. The devices have a usable receive sensitivity of 0 to -43dB, which allows the device to operate on cables over 2km in length. The receiveside framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, AIS, and Remote Alarm. If needed, the receiveside elastic store can be enabled to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock, which is provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz clock or a 1.544MHz clock. The transmit-side framer is totally independent from the receive side in both the clock requirements and characteristics. Data off a backplane can be passed through a transmit-side elastic store if necessary. The transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission. Reader's Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125ms frame, there are 32 eight-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1, time slot 1 is identical to Channel 2, and so on. Each time slot (or channel) is made up of eight bits, which are numbered 1 to 8. Bit number 1 is the most significant bit (MSB) and is transmitted first. Bit number 8 is the least significant bit (LSB) and is transmitted last. The term "locked" refers to two clock signals that are phase or frequency locked, or derived from a common clock (i.e., a 1.544MHz clock may be locked to a 2.048MHz clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations are used: NAME FAS CAS MF Si CRC4 CCS Sa E-Bit FUNCTION Frame-Alignment Signal Channel-Associated Signaling Multiframe International Bits Cyclical Redundancy Check Common-Channel Signaling Additional Bits CRC4 Error Bits
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1.2.
Document Revision History
DESCRIPTION Initial release Corrected TSYSCLK and RSYSCLK timing and added 4.096MHz and 8.192MHz timing Corrected definition and label of TUDR bit in the THIR register. Corrected address of IBO register in text. Added Receive Monitor Mode section Added section on Protected Interfaces Corrected pin number and description of FMS in JTAG section Added list of tables and figures Added 10mF cap to interface examples Corrected definition of DS in pin description. Typo corrected in JTAG Test Access Port Pins. Added note to the Receive Information Register, FAS Resync Criteria Met. Corrected Figures 20-1, 20-2, 20-3 with respect to CS. Corrected typo in Figure 18-14 (RCR1.1 reference corrected). Corrected formatting issues.
REVISION 012799 012899 020399 021199 040199 041599 050799 072999 091499 092399 072401
021004
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CI
RPOSI RCLKI RNEGI RNEGO RCLKO RPOSO
XTALD 8XCLK RCL RCLK RLOS/LOTC HDLC/BOC Controller Sa / DS0 MUX LIUC Timing Control Signaling Buffer
RSYSCLK
2. BLOCK DIAGRAM
32.768MHz
MCLK VCO / PLL Receive Side Framer DATA CLOCK SYNC Elastic Store 16.384 MHz 8.192MHz Clock Synthesizer 8MCLK RLINK RLCLK RCHBLK RCHCLK RSIGF RSIG RSER Interleave Bus RSYSCLK RSYNC RMSYNC RFSYNC RDATA TSYNC TDATA TESO Elastic Store Hardware Signaling Insertion LOTC MUX HDLC/BOC Controller Sa / DS0 TSSYNC TSYSCLK Interleave Bus TSER TSIG TCLK Timing Control TCHBLK TCHCLK TLINK TLCLK
7 8
RRING
Figure 2-1. DS21354/554 Block Diagram
Receive Line I/F Clock / Data Recovery
RTIP
Remote Loopback Sync Control
DS21354/ DS21554
Jitter Attenuator Either transmit or receive path
Local Loopback
Framer Loopback
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Transmit Side Formatter SYNC CLOCK DATA Sa MUX Parallel & Test Control Port (routed to all blocks) INT* TEST LIUC JTDO JTDI TNEGI TCLKI TPOSI TPOSO TCLKO TNEGO A0 to A6 MUX D0 to D7 / AD0 to AD7 ALE(AS) / A7 RD*(DS*) WR*(R/W*) BTS CS*
TRING
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Transmit Line I/F
TTIP
JTAG PORT
CO
JRST*
JTCLK JTMS
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
3. PIN DESCRIPTION
Table 3-1. Pin Description Sorted by Pin Number
PIN 1 2 3 4 5 6 7 8, 9, 15, 23, 26, 27, 28 10 11 12 13 14 16 17 18 19, 20, 24 21 22 25 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44, 61, 81,83 45, 60, 80, 84 46 47 48 NAME RCHBLK JTMS 8MCLK JTCLK JTRST RCL JTDI N.C. JTDO BTS LIUC 8XCLK TEST RTIP RRING RVDD RVSS MCLK XTALD INT TTIP TVSS TVDD TRING TCHBLK TLCLK TLINK CI TSYNC TPOSI TNEGI TCLKI TCLKO TNEGO TPOSO DVDD DVSS TCLK TSER TSIG TYPE O I O I I O I -- O I I O I I I - - I O O O - - O O O I I I/O I I I O O O -- -- I I I FUNCTION Receive Channel Block IEEE 1149.1 Test Mode Select 8.192 MHz Clock IEEE 1149.1 Test Clock Signal IEEE 1149.1 Test Reset, Active Low Receive Carrier Loss IEEE 1149.1 Test Data Input No Connect. Do not connect any signal to this pin. IEEE 1149.1 Test Data Output Bus Type Select Line Interface Connect Eight Times Clock Test Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Receive Analog Signal Ground Master Clock Input Quartz Crystal Driver Interrupt, Active Low Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Channel Block Transmit Link Clock Transmit Link Data Carry In Transmit Sync Transmit Positive Data Input Transmit Negative Data Input Transmit Clock Input Transmit Clock Output Transmit Negative Data Output Transmit Positive Data Output Digital Positive Supply Digital Signal Ground Transmit Clock Transmit Serial Data Transmit Signaling Input
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PIN 49 50 51 52 53 54 55 56 57 58 59 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 82 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
NAME TESO TDATA TSYSCLK TSSYNC TCHCLK CO MUX D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE (AS)/A7 RD (DS) CS FMS WR (R/W) RLINK RLCLK RCLK RDATA RPOSI RNEGI RCLKI RCLKO RNEGO RPOSO RCHCLK RSIGF RSIG RSER RMSYNC RFSYNC RSYNC RLOS/LOTC RSYSCLK
TYPE O I I I O O I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I O O O O I I I O O O O O O O O O I/O O I
FUNCTION Transmit Elastic Store Output Transmit Data Transmit System Clock Transmit System Sync Transmit Channel Clock Carry Out Bus Operation Data Bus Bit0/Address/Data Bus Bit 0 Data Bus Bit1/Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus 2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Latch Enable/Address Bus Bit 7 Read Input (Data Strobe), Active Low Chip Select, Active Low Framer Mode Select Write Input (Read/Write), Active Low Receive Link Data Receive Link Clock Receive Clock Receive Data Receive Positive Data Input Receive Negative Data Input Receive Clock Input Receive Clock Output Receive Negative Data Output Receive Positive Data Output Receive Channel Clock Receive Signaling Freeze Output Receive Signaling Output Receive Serial Data Receive Multiframe Sync Receive Frame Sync Receive Sync Receive Loss Of Sync/ Loss Of Transmit Clock Receive System Clock
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Table 3-2. Pin Description by Symbol
PIN 3 13 66 67 68 69 70 71 72 73 11 36 54 75 56 57 58 59 62 63 64 65 44, 61, 81, 83 45, 60, 80, 84 76 25 4 7 10 2 5 12 21 55 8, 9, 15, 23, 26, 27, 28 1 92 6 82 88 89 74 85 97 79 NAME 8MCLK 8XCLK A0 A1 A2 A3 A4 A5 A6 ALE (AS)/A7 BTS CI CO CS D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 DVDD DVSS FMS INT JTCLK JTDI JTDO JTMS JTRST LIUC MCLK MUX N.C. RCHBLK RCHCLK RCL RCLK RCLKI RCLKO RD (DS) RDATA RFSYNC RLCLK TYPE O O I I I I I I I I I I O I I/O I/O I/O I/O I/O I/O I/O I/O -- -- I O I I O I I I I I -- O O O O I O I O O O FUNCTION 8.192MHz Clock Eight-Times Clock Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Latch Enable/Address Bus Bit 7 Bus Type Select Carry In Carry Out Chip Select, Active Low Data Bus Bit0/ Address/Data Bus Bit 0 Data Bus Bit1/ Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus 2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 Digital Positive Supply Digital Signal Ground Framer Mode Select Interrupt IEEE 1149.1 Test Clock Signal IEEE 1149.1 Test Data Input IEEE 1149.1 Test Data Output IEEE 1149.1 Test Mode Select IEEE 1149.1 Test Reset, Active Low Line Interface Connect Master Clock Input Bus Operation No Connect. Do not connect any signal to this pin. Receive Channel Block Receive Channel Clock Receive Carrier Loss Receive Clock Receive Clock Input Receive Clock Output Read Input (Data Strobe), Active Low Receive Data Receive Frame Sync Receive Link Clock
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PIN 78 99 96 87 90 86 91 17 95 94 93 98 100 16 18 19, 20, 24 33 53 46 40 41 50 49 14 34 35 39 42 38 43 32 47 48 52 37 51 29 31 30 77 22
NAME RLINK RLOS/LOTC RMSYNC RNEGI RNEGO RPOSI RPOSO RRING RSER RSIG RSIGF RSYNC RSYSCLK RTIP RVDD RVSS TCHBLK TCHCLK TCLK TCLKI TCLKO TDATA TESO TEST TLCLK TLINK TNEGI TNEGO TPOSI TPOSO TRING TSER TSIG TSSYNC TSYNC TSYSCLK TTIP TVDD TVSS WR (R/W) XTALD
TYPE O O O I O I O I O O O I/O I I -- -- O O I I O I O I O I I O I O O I I I I/O I O -- -- I O
FUNCTION Receive Link Data Receive Loss of Sync/Loss of Transmit Clock Receive Multiframe Sync Receive Negative Data Input Receive Negative Data Output Receive Positive Data Input Receive Positive Data Output Receive Analog Ring Input Receive Serial Data Receive Signaling Output Receive Signaling Freeze Output Receive Sync Receive System Clock Receive Analog Tip Input Receive Analog Positive Supply Receive Analog Signal Ground Transmit Channel Block Transmit Channel Clock Transmit Clock Transmit Clock Input Transmit Clock Output Transmit Data Transmit Elastic Store Output Test Transmit Link Clock Transmit Link Data Transmit Negative Data Input Transmit Negative Data Output Transmit Positive Data Input Transmit Positive Data Output Transmit Analog Ring Output Transmit Serial Data Transmit Signaling Input Transmit System Sync Transmit Sync Transmit System Clock Transmit Analog Tip Output Transmit Analog Positive Supply Transmit Analog Signal Ground Write Input (Read/Write), Active Low Quartz Crystal Driver
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3.1.
3.1.1.
Pin Function Description
Transmit-Side Pins
Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Signal Name: TCHCLK Signal Description: Transmit Channel Clock Signal Type: Output A 256kHz clock that pulses high during the LSB of each channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of channel data. Signal Name: TCHBLK Signal Description: Transmit Channel Block Signal Type: Output A user-programmable output that can be forced high or low during any of the 32 E1 channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 12 for details. Signal Name: TSYSCLK Signal Description: Transmit System Clock Signal Type: Input 1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the transmit-side elastic store function is enabled. Should be tied low in applications that do not use the transmit-side elastic store. See Section 17 for details on 4.096MHz and 8.192MHz operation using the Interleave Bus Option. Signal Name: TLCLK Signal Description: Transmit Link Clock Signal Type: Output 4kHz to 20kHz demand clock (Sa bits) for the TLINK input. See Section 17 for details.
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Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section 13 for details. Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR1.1, the DS21354/DS21554 can be programmed to output either a frame or multiframe pulse at this pin. This pin can also be configured as an input via TCR1.0. See Section 18 for details. Signal Name: TSSYNC Signal Description: Transmit System Sync Signal Type: Input Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store. Signal Name: TSIG Signal Description: Transmit Signaling Input Signal Type: Input When enabled, this input will sample signaling bits for insertion into outgoing PCM E1 data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. Signal Name: TESO Signal Description: Transmit Elastic Store Data Output Signal Type: Output Updated on the rising edge of TCLK with data out of the transmit-side elastic store whether the elastic store is enabled or not. This pin is normally tied to TDATA. Signal Name: TDATA Signal Description: Transmit Data Signal Type: Input Sampled on the falling edge of TCLK with data to be clocked through the transmit-side formatter. This pin is normally tied to TESO. Signal Name: TPOSO Signal Description: Transmit Positive Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source NRZ data via the Output Data Format (TCR2.2) control bit. This pin is normally tied to TPOSI.
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Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to TNEGI. Signal Name: TCLKO Signal Description: Transmit Clock Output Signal Type: Output Buffered output of signal that is clocking data through the transmit-side formatter. This pin is normally tied to TCLKI. Signal Name: TPOSI Signal Description: Transmit Positive Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Signal Name: TNEGI Signal Description: Transmit Negative Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Signal Name: TCLKI Signal Description: Transmit Clock Input Signal Type: Input Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high.
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3.1.2.
Receive-Side Pins
Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with the fully recovered E1 data stream on the rising edge of RCLK. Signal Name: RLCLK Signal Description: Receive Link Clock Signal Type: Output 4kHz to 20kHz clock (Sa bits) for the RLINK output. See Section 13 for details. Signal Name: RCLK Signal Description: Receive Clock Signal Type: Output 2.048MHz clock that is used to clock data through the receive-side framer. Signal Name: RCHCLK Signal Description: Receive Channel Clock Signal Type: Output A 256kHz clock that pulses high during the LSB of each channel. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel to serial conversion of channel data. Signal Name: RCHBLK Signal Description: Receive Channel Block Signal Type: Output A user-programmable output that can be forced high or low during any of the 32 E1 channels. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384kbps service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 10 for details. Signal Name: RSER Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled. Signal Name: RSYNC Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin that identifies either frame or CAS/CRC multiframe boundaries. If the receive-side elastic store is enabled, then this pin can be enabled to be an input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
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Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output If the receive-side elastic store is enabled, an extracted pulse, one RSYSCLK wide, is output at this pin that identifies multiframe boundaries. If the receive-side elastic store is disabled, then this output will output multiframe boundaries associated with RCLK. Signal Name: RDATA Signal Description: Receive Data Signal Type: Output Updated on the rising edge of RCLK with the data out of the receive-side framer. Signal Name: RSYSCLK Signal Description: Receive System Clock Signal Type: Input 1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store function is enabled. Should be tied low in applications that do not use the receive-side elastic store. See Section 17 for details on 4.096MHz and 8.192MHz operation using the Interleave Bus Option. Signal Name: RSIG Signal Description: Receive Signaling Output Signal Type: Output Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled. Signal Name: RLOS/LOTC Signal Description: Receive Loss of Sync / Loss of Transmit Clock Signal Type: Output A dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5ms. Signal Name: RCL Signal Description: Receive Carrier Loss Signal Type: Output Set high when the line interface detects a carrier loss. Signal Name: RSIGF Signal Description: Receive Signaling Freeze Signal Type: Output Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition.
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Signal Name: 8MCLK Signal Description: 8MHz Clock Signal Type: Output An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSO Signal Description: Receive Positive Data Input Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RNEGO Signal Description: Receive Negative Data Input Signal Type: Output Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI. Signal Name: RCLKO Signal Description: Receive Clock Output Signal Type: Output Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI. Signal Name: RPOSI Signal Description: Receive Positive Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high. Signal Name: RNEGI Signal Description: Receive Negative Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high. Signal Name: RCLKI Signal Description: Receive Clock Input Signal Type: Input Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.
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3.1.3.
Parallel Control Port Pins
Signal Name: INT Signal Description: Interrupt Signal Type: Output Active-low, open-drain output that flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. Signal Name: FMS Signal Description: Framer Mode Select Signal Type: Input Selects the DS2154 mode when high or the DS21354/DS21554 mode when low. If high, the JTRST is internally pulled low. If low, JTRST has normal JTAG functionality. This pin has a 10kW pullup resistor. Signal Name: TEST Signal Description: Tri-State Control Signal Type: Input Set high to tri-state all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: AD0 to AD7 Signal Description: Data Bus [D0 to D7] or Address/Data Bus Signal Type: Input In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed address/data bus. Signal Name: A0 to A6 Signal Description: Address Bus Signal Type: Input In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low. Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS), and WR (R/W) pins. If BTS = 1, then these pins assume the function listed in parentheses ().
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Signal Name: RD (DS) Signal Description: Read Input--Data Strobe Signal Type: Input In Intel Mode, RD determines when data is read from the device. In Motorola Mode, DS is used to write to the device. See the Bus Timing Diagrams section. CS Signal Name: Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS is an active-low signal. Signal Name: ALE (AS)/A7 Signal Description: Address Latch Enable (Address Strobe) or A7 Signal Type: Input In nonmultiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus on a positive-going edge. Signal Name: WR (R/W) Signal Description: Write Input (Read/Write) Signal Type: Input WR is an active-low signal.
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3.1.4.
JTAG Test Access Port Pins
JTRST Signal Name: Signal Description: IEEE 1149.1 Test Reset Signal Type: Input This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test access port features. This pin has a 10kW pullup resistor. When FMS = 1, this pin is tied low internally. Tie JTRST low if JTAG is not used and the framer is in DS21354/DS21554 mode (FMS low). Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10kW pullup resistor. Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor. Signal Name: JTDO Signal Description: IEEE 1149.1 Test Data Output Signal Type: Output Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.
3.1.5. Interleave Bus Operation Pins
Signal Name: CI Signal Description: Carry In Signal Type: Input A rising edge on this pin causes RSER and RSIG to come out of high-Z state and TSER and TSIG to start sampling on the next rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of data. This pin has a 10kW pullup resistor. Signal Name: CO Signal Description: Carry Out Signal Type: Output An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER and RSIG.
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3.1.6.
Line Interface Pins
Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 2.048MHz (50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal of 2.048MHz may be applied across MCLK and XTALD instead of the TTL level clock source. Signal Name: XTALD Signal Description: Quartz Crystal Driver Signal Type: Output A quartz crystal of 2.048MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is applied at MCLK. Signal Name: 8XCLK Signal Description: Eight-Times Clock Signal Type: Output A 16.384MHz clock that is frequency locked to the 2.048MHz clock provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally disabled via TEST2 register if not needed. Signal Name: LIUC Signal Description: Line Interface Connect Signal Type: Input Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low. Signal Name: RTIP and RRING Signal Description: Receive Tip and Ring Signal Type: Input Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the E1 line. See Section 15 for details. Signal Name: TTIP and TRING Signal Description: Transmit Tip and Ring Signal Type: Output Analog line-driver outputs. These pins connect via a step-up transformer to the E1 line. See Section 15 for details.
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3.1.7.
Supply Pins
Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 5.0V 5% (DS21554) or 3.3V 5% (DS21354). Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 5.0V 5% (DS21554) or 3.3V 5% (DS21354). Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 5.0V 5% (DS21554) or 3.3V 5% (DS21354). Should be tied to the RVDD and DVDD pins. Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply 0.0V. Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0.0V. Should be tied to DVSS and TVSS. Signal Name: TVSS Signal Description: Transmit Analog Signal Ground Signal Type: Supply 0.0V. Should be tied to DVSS and RVSS.
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4. PARALLEL PORT
The DS21354/DS21554 are controlled through either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing is selected; if tied high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section 18 for more details. 4.1.
Register Map
Table 4-1. Register Map Sorted by Address
ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 TYPE R R R R R R R/W R/W R/W -- -- -- -- -- -- R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W REGISTER BPV or Code Violation Count 1 BPV or Code Violation Count 2 CRC4 Error Count 1/FAS Error Count 1 CRC4 Error Count 2 E-Bit Count 1/FAS Error Count 2 E-Bit Count 2 Status 1 Status 2 Receive Information Not used Not used Not used Not used Not used Not used Device ID Receive Control 1 Receive Control 2 Transmit Control 1 Transmit Control 2 Common Control 1 Test 1 Interrupt Mask 1 Interrupt Mask 2 Line Interface Control Register Test 2 Common Control 2 Common Control 3 Transmit Sa Bit Control Common Control 6 Synchronizer Status Receive Non-Align Frame Transmit Align Frame Transmit Non-Align Frame Transmit Channel Blocking 1 Transmit Channel Blocking 2 Transmit Channel Blocking 3
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NAME VCR1 VCR2 CRCCR1 CRCCR2 EBCR1 EBCR2 SR1 SR2 RIR (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) IDR RCR1 RCR2 TCR1 TCR2 CCR1 TEST1 (set to 00h) IMR1 IMR2 LICR TEST2 (set to 00h) CCR2 CCR3 TSaCR CCR6 SSR RNAF TAF TNAF TCBR1 TCBR2 TCBR3
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54
TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER Transmit Channel Blocking 4 Transmit Idle 1 Transmit Idle 2 Transmit Idle 3 Transmit Idle 4 Transmit Idle Definition Receive Channel Blocking 1 Receive Channel Blocking 2 Receive Channel Blocking 3 Receive Channel Blocking 4 Receive Align Frame Receive Signaling 1 Receive Signaling 2 Receive Signaling 3 Receive Signaling 4 Receive Signaling 5 Receive Signaling 6 Receive Signaling 7 Receive Signaling 8 Receive Signaling 9 Receive Signaling 10 Receive Signaling 11 Receive Signaling 12 Receive Signaling 13 Receive Signaling 14 Receive Signaling 15 Receive Signaling 16 Transmit Signaling 1 Transmit Signaling 2 Transmit Signaling 3 Transmit Signaling 4 Transmit Signaling 5 Transmit Signaling 6 Transmit Signaling 7 Transmit Signaling 8 Transmit Signaling 9 Transmit Signaling 10 Transmit Signaling 11 Transmit Signaling 12 Transmit Signaling 13 Transmit Signaling 14 Transmit Signaling 15 Transmit Signaling 16 Transmit Si Bits Align Frame Transmit Si Bits Non-Align Frame Transmit Remote Alarm Bits Transmit Sa4 Bits Transmit Sa5 Bits
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NAME TCBR4 TIR1 TIR2 TIR3 TIR4 TIDR RCBR1 RCBR2 RCBR3 RCBR4 RAF RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TSiAF TSiNAF TRA TSa4 TSa5
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84
TYPE R/W R/W R/W R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER Transmit Sa6 Bits Transmit Sa7 Bits Transmit Sa8 Bits Receive Si Bits Align Frame Receive Si Bits Non-Align Frame Receive Remote Alarm Bits Receive Sa4 Bits Receive Sa5 Bits Receive Sa6 Bits Receive Sa7 Bits Receive Sa8 Bits Transmit Channel 1 Transmit Channel 2 Transmit Channel 3 Transmit Channel 4 Transmit Channel 5 Transmit Channel 6 Transmit Channel 7 Transmit Channel 8 Transmit Channel 9 Transmit Channel 10 Transmit Channel 11 Transmit Channel 12 Transmit Channel 13 Transmit Channel 14 Transmit Channel 15 Transmit Channel 16 Transmit Channel 17 Transmit Channel 18 Transmit Channel 19 Transmit Channel 20 Transmit Channel 21 Transmit Channel 22 Transmit Channel 23 Transmit Channel 24 Transmit Channel 25 Transmit Channel 26 Transmit Channel 27 Transmit Channel 28 Transmit Channel 29 Transmit Channel 30 Transmit Channel 31 Transmit Channel 32 Receive Channel 1 Receive Channel 2 Receive Channel 3 Receive Channel 4 Receive Channel 5
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NAME TSa6 TSa7 TSa8 RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TC17 TC18 TC19 TC20 TC21 TC22 TC23 TC24 TC25 TC26 TC27 TC28 TC29 TC30 TC31 TC32 RC1 RC2 RC3 RC4 RC5
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4
TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W -- -- -- R/W R/W R/W R/W R/W
REGISTER Receive Channel 6 Receive Channel 7 Receive Channel 8 Receive Channel 9 Receive Channel 10 Receive Channel 11 Receive Channel 12 Receive Channel 13 Receive Channel 14 Receive Channel 15 Receive Channel 16 Receive Channel 17 Receive Channel 18 Receive Channel 19 Receive Channel 20 Receive Channel 21 Receive Channel 22 Receive Channel 23 Receive Channel 24 Receive Channel 25 Receive Channel 26 Receive Channel 27 Receive Channel 28 Receive Channel 29 Receive Channel 30 Receive Channel 31 Receive Channel 32 Transmit Channel Control 1 Transmit Channel Control 2 Transmit Channel Control 3 Transmit Channel Control 4 Receive Channel Control 1 Receive Channel Control 2 Receive Channel Control 3 Receive Channel Control 4 Common Control 4 Transmit DS0 Monitor Common Control 5 Receive DS0 Monitor Test 3 Not used Not used Not used HDLC Control Register HDLC Status Register HDLC Interrupt Mask Register Receive HDLC Information Register Receive HDLC FIFO Register
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NAME RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC18 RC19 RC20 RC21 RC22 RC23 RC24 RC25 RC26 RC27 RC28 RC29 RC30 RC31 RC32 TCC1 TCC2 TCC3 TCC4 RCC1 RCC2 RCC3 RCC4 CCR4 TDS0M CCR5 RDS0M TEST3 (set to 00h) (set to 00h) (set to 00h) HCR HSR HIMR RHIR RHFR
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS B5 B6 B7 B8 B9 BA BB BC BD BE BF
Note 1: Note 2:
TYPE R/W R/W R/W R/W R/W R/W R/W -- -- -- --
REGISTER Interleave Bus Operation Register Transmit HDLC Information Register Transmit HDLC FIFO Register Receive HDLC DS0 Control Register 1 Receive HDLC DS0 Control Register 2 Transmit HDLC DS0 Control Register 1 Transmit HDLC DS0 Control Register 2 Not used Not used Not used Not used
NAME IBO THIR THFR RDC1 RDC2 TDC1 TDC2 (set to 00h) (set to 00h) (set to 00h) (set to 00h)
Test Registers are used only by the factory. These registers must be cleared (set to all zeros) on power-up initialization to ensure proper operation. Register banks Cxh, Dxh, Exh, and Fxh are not accessible.
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5. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21354/DS21554 is configured via a set of 10 control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers need only to be accessed when there is a change in the system configuration. There are two receive control registers (RCR1 and RCR2), two transmit control registers (TCR1 and TCR2), and six common control registers (CCR1 to CCR6). Each of the 10 registers is described in this section. There is a device identification register (IDR) at address 0Fh. The MSB of this read-only register is fixed to a one, indicating that an E1 SCT is present. The next three MSBs are used to indicate which E1 device is present--DS2154, DS21354, or DS21554. The T1 pin-for-pin compatible SCTs have a logic zero in the MSB position with the following three MSBs indicating which T1 SCT is present--DS2152, DS21352, or DS21552. Table 5-1 represents the possible variations of these bits and the associated SCT. Table 5-1. Device ID Bit Map SCT DS2152 DS21352 DS21552 DS2154 DS21354 DS21554 T1/E1 0 0 0 1 1 1 BIT 6 0 0 0 0 0 0 BIT 5 0 0 1 0 0 1 BIT 4 0 1 0 0 1 0
The lower four bits of the IDR are used to display the die revision of the chip. The test registers at addresses 09, 15, 19, and AC hex are used by the factory in testing the DS21354/DS21554. On power-up, the test registers should be set to 00h in order for the DS21354/DS21554 to operate properly. Certain bits of TEST3 are used to select monitor mode functions. Please see Section 15.5 for further details. 5.1. Power-Up Sequence On power-up, after the supplies are stable the DS21354/DS21554 should be configured for operation by writing to all the internal registers (this includes setting the test registers to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.7) should be toggled from zero to one to reset the line-interface circuitry (it will take the device about 40ms to recover from the LIRST bit being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bits (CCR6.0 and CCR6.1) should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled).
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IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex) (MSB) T1E1 Bit 6 Bit 5 Bit 4 ID3 ID2 SYMBOL T1E1 Bit 6 Bit 5 Bit 4 ID3 ID2 ID1 ID0 POSITION IDR.7 IDR.6 IDR.5 IDR.4 IDR.3 IDR.1 IDR.2 IDR.0
ID1
(LSB) ID0
NAME AND DESCRIPTION T1 or E1 Chip Determination Bit. Set to 1. 0 = T1 chip 1 = E1 chip Bit 6. See Table 5-1. Bit 5. See Table 5-1. Bit 4. See Table 5-1. Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2. Chip Revision Bit 1. Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10 Hex) (MSB) RSMF RSM RSIO -- -- FRC SYMBOL RSMF POSITION RCR1.7
SYNCE
(LSB) RESYNC
RSM RSIO -- -- FRC
RCR1.6 RCR1.5 RCR1.4 RCR1.3 RCR1.2
SYNCE RESYNC
RCR1.1 RCR1.0
NAME AND DESCRIPTION RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the multiframe mode (RCR1.6=1). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries RSYNC Mode Select. 0 = frame mode (see the timing in Section 18) 1 = multiframe mode (see the timing in Section 18) RSYNC I/O Select. (Note: this bit must be set to zero when RCR2.1=0). 0 = RSYNC is an output (depends on RCR1.6) 1 = RSYNC is an input (only valid if elastic store enabled) Not Assigned. Should be set to zero when written. Not Assigned. Should be set to zero when written. Frame Resync Criteria. 0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times Sync Enable. 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.
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5.2. Synchronization And Resynchronization Once synchronization is accomplished there are certain criteria that can cause a resynchronization. These criteria are detailed in Table 5-2. Also see Figure 18-14 for a flow chart of the synchronization process. Table 5-2. SYNC/RESYNC Criteria FRAME OR MULTIFRAME LEVEL FAS SYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 RESYNC CRITERIA Three consecutive incorrect FAS received Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non-FAS received 915 or more CRC4 codewords out of 1000 received in error Two consecutive MF alignment words received in error ITU SPEC. G.706 4.1.1 4.1.2
CRC4 CAS
Two valid MF alignment words found within 8 ms Valid MF alignment word found and previous time slot 16 contains code other than all zeros
G.706 4.2 and 4.3.2 G.732 5.2
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RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex) (MSB) Sa8S Sa7S Sa6S Sa5S Sa4S RBCS SYMBOL Sa8S Sa7S Sa6S Sa5S Sa4S RBCS RESE -- POSITION RCR2.7 RCR2.6 RCR2.5 RCR2.4 RCR2.3 RCR2.2 RCR2.1 RCR2.0
RESE
(LSB) --
NAME AND DESCRIPTION Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit position; set to zero to force RLCLK low during Sa8 bit position. See Section 18.1 for timing details. Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit position; set to zero to force RLCLK low during Sa7 bit position. See Section 18.1 for timing details. Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit position; set to zero to force RLCLK low during Sa6 bit position. See Section 18.1 for timing details. Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit position; set to zero to force RLCLK low during Sa5 bit position. See Section 18.1 for timing details. Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit position; set to zero to force RLCLK low during Sa4 bit position. See Section 18.1 for timing details. Receive-Side Backplane Clock Select. 0 = if RSYSCLK is 1.544 MHz 1 = if RSYSCLK is 2.048/4.096/8.192 MHz Receive-Side Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Not Assigned. Should be set to zero when written.
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex) (MSB) ODF TFPT T16S TUA1 TSiS TSA1 SYMBOL ODF POSITION TCR1.7
TSM
(LSB) TSIO
TFPT
TCR1.6
T16S TUA1
TCR1.5 TCR1.4
TSiS
TCR1.3
TSA1 TSM TSIO
TCR1.2 TCR1.1 TCR1.0
NAME AND DESCRIPTION Output Data Format. 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO=0 Transmit Time Slot 0 Pass Through. 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER Transmit Time slot 16 Data Select. 0 = sample time slot 16 at TSER pin 1 = source time slot 16 from TS0 to TS15 registers Transmit Unframed All Ones. 0 = transmit data normally 1 = transmit an unframed all one's code at TPOSO and TNEGO Transmit International Bit Select. 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR1.6 must be set to 0) Transmit Signaling All Ones. 0 = normal operation 1 = force time slot 16 in every frame to all ones TSYNC Mode Select. 0 = frame mode (see the timing in Section 18.2) 1 = CAS and CRC4 multiframe mode (see the timing in Section 18.2) TSYNC I/O Select. 0 = TSYNC is an input 1 = TSYNC is an output
Note: See Figure 18-15 for more details about how the Transmit Control Registers affect the operation of the DS21354/DS21554.
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex) (MSB) Sa8S Sa7S Sa6S Sa5S Sa4S ODM SYMBOL Sa8S Sa7S Sa6S Sa5S Sa4S ODM AEBE PF POSITION TCR2.7 TCR2.6 TCR2.5 TCR2.4 TCR2.3 TCR2.2 TCR2.1 TCR2.0
AEBE
(LSB) PF
NAME AND DESCRIPTION Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; to zero to not source the Sa8 bit. See Section 18.2 for timing details. Sa7 Bit Select. Set to one to source the Sa7 bit from the TLINK pin; to zero to not source the Sa7 bit. See Section 18.2 for timing details. Sa6 Bit Select. Set to one to source the Sa6 bit from the TLINK pin; to zero to not source the Sa6 bit. See Section 18.2 for timing details. Sa5 Bit Select. Set to one to source the Sa5 bit from the TLINK pin; to zero to not source the Sa5 bit. See Section 18.2 for timing details. Sa4 Bit Select. Set to one to source the Sa4 bit from the TLINK pin; to zero to not source the Sa4 bit. See Section 18.2 for timing details. Output Data Mode. 0 = pulses at TPOSO and TNEGO are one full TCLKO period wide 1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide Automatic E-Bit Enable. 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Function of RLOS/LOTC Pin. 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC)
set set set set set
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CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex) (MSB) FLB THDB3 TG802 TCRC4 RSM RHDB3 SYMBOL FLB THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4 POSITION CCR1.7 CCR1.6 CCR1.5 CCR1.4 CCR1.3 CCR1.2 CCR1.1 CCR1.0
RG802
(LSB) RCRC4
NAME AND DESCRIPTION Framer Loopback. 0 = loopback disabled 1 = loopback enabled Transmit HDB3 Enable. 0 = HDB3 disabled 1 = HDB3 enabled Transmit G.802 Enable. See Section 18 for details. 0 = do not force TCHBLK high during bit 1 of time slot 26 1 = force TCHBLK high during bit 1 of time slot 26 Transmit CRC4 Enable. 0 = CRC4 disabled 1 = CRC4 enabled Receive Signaling Mode Select. 0 = CAS signaling mode 1 = CCS signaling mode Receive HDB3 Enable. 0 = HDB3 disabled 1 = HDB3 enabled Receive G.802 Enable. See Section 18 for details. 0 = do not force RCHBLK high during bit 1 of time slot 26 1=force RCHBLK high during bit 1 of time slot 26 Receive CRC4 Enable. 0 = CRC4 disabled 1 = CRC4 enabled
5.3. Framer Loopback When CCR1.7 is set to one, the DS21354/DS21554 enter a framer loopback (FLB) mode. See Figure 2-1 for more details. This loopback is useful in testing and debugging applications. In FLB, the SCT will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1) Data will be transmitted as normal at TPOSO and TNEGO. 2) Data input via RPOSI and RNEGI will be ignored. 3) The RCLK output will be replaced with the TCLK input.
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CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex) (MSB) ECUS VCRFS AAIS ARA RSERC LOTCMC SYMBOL ECUS VCRFS AAIS ARA RSERC POSITION CCR2.7 CCR2.6 CCR2.5 CCR2.4 CCR2.3
RFF
(LSB) RFE
LOTCMC
CCR2.2
RFF
CCR2.1
RFE
CCR2.0
NAME AND DESCRIPTION Error Counter Update Select. See Section 7 for details. 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) VCR Function Select. See Section 7.1 for details. 0 = count BiPolar Violations (BPVs) 1 = count Code Violations (CVs) Automatic Transmit AIS Generation. 0 = disabled 1 = enabled Automatic Remote Alarm Generation. 0 = disabled 1 = enabled RSER Control. 0 = allow RSER to output data as received under all conditions 1 = force RSER to one under loss of frame alignment conditions Loss of Transmit Clock Mux Control. Determines whether the transmit-side formatter should switch to the ever-present RCLKO if the TCLK should fail to transition (see Figure 2-1). 0 = do not switch to RCLKO if TCLK stops 1 = switch to RCLKO if TCLK stops Receive Force Freeze. Freezes receive-side signaling at RSIG (and TS16 in RSER if CCR3.3 = 1); will override Receive Freeze Enable (RFE). See Section 9 for details. 0 = do not force a freeze event 1 = force a freeze event Receive Freeze Enable. See Section 9 for details. 0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signaling data at RSIG (and TS16 in RSER if CCR3.3 = 1).
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5.4. Automatic Alarm Generation The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer will either force an AIS alarm. When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one's) reception, or loss of receive carrier (or signal) or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, then the framer will either transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant Remote Alarm will be transmitted if the DS21354/DS21554 cannot find CRC4 multiframe synchronization within 400ms as per G.706.
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CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex) (MSB) TESE TCBFS TIRFS -- RSRE THSE SYMBOL TESE TCBFS POSITION CCR3.7 CCR3.6
TBCS
(LSB) RCLA
TIRFS RSRE
CCR3.5 CCR3.4 CCR3.3
THSE
CCR3.2
TBCS RCLA
CCR3.1 CCR3.0
NAME AND DESCRIPTION Transmit-Side Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Transmit Channel Blocking Registers (TCBR) Function Select. 0 = TCBRs define the operation of the TCHBLK output pin 1 = TCBRs define which signaling bits are to be inserted Transmit Idle Registers (TIR) Function Select. See Section 10.1 for details. 0 = TIRs define in which channels to insert idle code 1 = TIRs define in which channels to insert data from RSER (i.e., PerCannel Loopback function) Not Assigned. Should be set to zero when written to. Receive-Side Signaling Reinsertion Enable. See Section 10.2 for details. 0 = do not reinsert signaling bits into the data stream presented at the RSER pin 1 = reinsert the signaling bits into data stream presented at the RSER pin Transmit-Side Hardware Signaling Insertion Enable. See Section 10.1 for details. 0 = do not insert signaling from the TSIG pin into the data stream presented at the TSER pin 1 = insert signaling from the TSIG pin into the data stream presented at the TSER pin Transmit-Side Backplane Clock Select. 0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.048MHz/4.096MHz/8.192MHz Receive Carrier Loss (RCL) Alternate Criteria. 0 = RCL declared upon 255 consecutive zeros (125ms) 1 = RCL declared upon 2048 consecutive zeros (1ms)
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CCR4: COMMON CONTROL REGISTER 4 (Address = A8 Hex) (MSB) RLB LLB LIAIS TCM4 TCM3 TCM2 SYMBOL RLB LLB POSITION CCR4.7 CCR4.6
TCM1
(LSB) TCM0
LIAIS
CCR4.5
TCM4 TCM3 TCM2 TCM1 TCM0
CCR4.4 CCR4.3 CCR4.2 CCR4.1 CCR4.0
NAME AND DESCRIPTION Remote Loopback. 0 = loopback disabled 1 = loopback enabled Local Loopback. 0 = loopback disabled 1 = loopback enabled Line Interface AIS Generation Enable. 0 = allow normal data from TPOSI/TNEGI to be transmitted at TTIP and TRING 1 = force unframed all ones to be transmitted at TTIP and TRING at the MCLK rate Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 8 for details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
5.5. Remote Loopback When CCR4.7 is set to a one, the SCT will be forced into remote loopback (RLB). In this loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data will continue to pass through the receive-side framer of the SCT as it would normally and the data from the transmit-side formatter will be ignored. Please see Figure 2-1 for more details. 5.6. Local Loopback When CCR4.6 is set to one, the SCT will be forced into local loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. Please see Figure 2-1 for more details.
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CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex) (MSB) LIRST RESA TESA RCM4 RCM3 RCM2 SYMBOL LIRST POSITION CCR5.7
RCM1
(LSB) RCM0
RESA
CCR5.6
TESA
CCR5.5
RCM4 RCM3 RCM2 RCM1 RCM0
CCR5.4 CCR5.3 CCR5.2 CCR5.1 CCR5.0
NAME AND DESCRIPTION Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Receive Elastic Store Align. Setting this bit from a zero to a one may force the receive elastic store's write/read pointers to a minim separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 12 for details. Transmit Elastic Store Align. Setting this bit from a zero to a one may force the transmit elastic store's write/read pointers to a minim separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 12 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 8 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
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CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex) (MSB) LIUODO CDIG LIUSI -- -- TCLKSRC SYMBOL POSITION
RESR
(LSB) TESR
LIUODO
CCR6.7
CDIG
CCR6.6
LIUSI
CCR6.5
-- --
CCR6.4 CCR6.3
TCLKSRC
CCR6.2
RESR
CCR6.1
TESR
CCR6.0
NAME AND DESCRIPTION Line Interface Open-Drain Option. This control bit determines whether the TTIP and TRING outputs will be open drain or not. The line driver outputs can be forced open drain to allow 6Vpeak pulses to be generated or to allow the creation of a very low power interface. 0 = allow TTIP and TRING to operate normally 1 = force the TTIP and TRING outputs to be open drain Customer Disconnect Indication Generator. This control bit determines whether the Line Interface will generate an unframed ...1010... pattern at TTIP and TRING instead of the normal data pattern. 0 = generate normal data at TTIP and TRING as input via TPOSI and TNEGI 1 = generates a ...1010... pattern at TTIP and TRING Line Interface G.703 Synchronization Interface Enable. This control bit determines whether the line receiver should handle a normal E1 signal (Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10 of G.703). This control has no affect on the line interface transmitter. 0 = line receiver configured to support a normal E1 signal 1 = line receiver configured to support a synchronization signal Not Assigned. Should be set to zero when written. Not Assigned. Should be set to zero when written. Transmit Clock Source Select. This function allows the user to internally select RCLK as the clock source for the transmit-side formatter. 0 = Source of transmit clock determined by CCR2.2 (LOTCMC) 1 = Force transmitter to internally switch to RCLK as source of transmit clock. Signal at TCLK pin is ignored Receive Elastic Store Reset. Setting this bit from a zero to a one will force the receive elastic store to a depth of one frame. Receive data is lost during the reset. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent reset. Transmit Elastic Store Reset. Setting this bit from a zero to a one will force the transmit elastic store to a depth of one frame. Transmit data is lost during the reset. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent reset.
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6. STATUS AND INFORMATION REGISTERS
The DS21354/DS21554 have a set of seven registers that contain information on the current real-time status of a framer--Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), Synchronizer Status Register (SSR), and a set of three registers for the on-board HDLC controller. The specific details on the four registers pertaining to the HDLC controller are covered in Section 14, but they operate the same as the other status registers in the device and this operation is described below. When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The Synchronizer Status Register contents are not latched. This means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still present). The user will always proceed a read of any of the SR1, SR2, and RIR registers with a write. The byte written to the register will inform the framer which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with the latest information. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically ANDed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21354/DS21554 with higher-order software languages. The SSR register operates differently than the other three. It is a read only register and it reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write. The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 14. The interrupts caused by alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). The alarm caused interrupts will force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 6-1). The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. The event caused interrupts will force the INT pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex) (MSB) TESF TESE JALT RESF RESE CRCRC SYMBOL TESF TESE JALT RESF RESE CRCRC POSITION RIR.7 RIR.6 RIR.5 RIR.4 RIR.3 RIR.2
FASRC
(LSB) CASRC
FASRC
RIR.1
CASRC
RIR.0
NAME AND DESCRIPTION Transmit-Side Elastic Store Full. Set when the transmit-side elastic store buffer fills and a frame is deleted. Transmit-Side Elastic Store Empty. Set when the transmit-side elastic store buffer empties and a frame is repeated. Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4-bits of its limit; useful for debugging jitter attenuation operation. Receive-Side Elastic Store Full. Set when the receive side elastic store buffer fills and a frame is deleted. Receive-Side Elastic Store Empty. Set when the receive side elastic store buffer empties and a frame is repeated. CRC Resync Criteria Met. Set when 915/1000 codewords are received in error. FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error. Note: During a CRC resync the FAS synchronizer is brought online to verify the FAS alignment. If during this process a FAS emulator exists, the FAS synchronizer may temporarily align to the emulator. The FASRC will go active indicating a search for a valid FAS has been activated. CAS Resync Criteria Met. Set when two consecutive CAS MF alignment words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex) (MSB) CSC5 CSC4 CSC3 CSC2 CSC0 FASSA SYMBOL CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA POSITION SSR.7 SSR.6 SSR.5 SSR.4 SSR.3 SSR.2 SSR.1 SSR.0
CASSA
(LSB) CRC4SA
NAME AND DESCRIPTION CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CRC4 Sync Counter Bit 4. CRC4 Sync Counter Bit 3. CRC4 Sync Counter Bit 2. CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next to LSB is not accessible. FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word.
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6.1. CRC4 Sync Counter The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter will roll over. SR1: STATUS REGISTER 1 (Address = 06 Hex) (MSB) RSA1 RDMA RSA0 RSLIP SYMBOL RSA1 POSITION SR1.7 (LSB) RLOS
RUA1
RRA
RCL
RDMA RSA0 RSLIP RUA1 RRA RCL RLOS
SR1.6 SR1.5 SR1.4 SR1.3 SR1.2 SR1.1 SR1.0
NAME AND DESCRIPTION Receive Signaling All Ones/Signaling Change. Set when the contents of time slot 16 contain less than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Both RSA1 and RSA0 will be set if a change in signaling is detected. Receive Distant MF Alarm. Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. Receive Signaling All Zeros/Signaling Change. Set when over a full MF, time slot 16 contains all zeros. Both RSA1 and RSA0 will be set if a change in signaling is detected. Receive-Side Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data. Receive Unframed All Ones. Set when an unframed all ones code is received at RPOSI and RNEGI. Receive Remote Alarm. Set when a remote alarm is received at RPOSI and RNEGI. Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1) consecutive zeros have been detected at RTIP and RRING. (Note: a receiver carrier loss based on data received at RPOSI and RNEGI is available in the HSR register) Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream.
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Table 6-1. Alarm Criteria ALARM RSA1 (Receive Signaling All Ones) RSA0 (Receive Signaling All Zeros) RDMA (Receive Distant Multiframe Alarm) RUA1 (Receive Unframed All Ones) RRA (Receive Remote Alarm) RCL (Receive Carrier Loss) SET CRITERIA over 16 consecutive frames (one full MF) time slot 16 contains less than three zeros over 16 consecutive frames (one full MF) time slot 16 contains all zeros bit 6 in time slot 16 of frame 0 set to one for two consecutive MF less than three zeros in two frames (512-bits) bit 3 of non-align frame set to one for three consecutive occasions 255 (or 2048) consecutive zeros received CLEAR CRITERIA over 16 consecutive frames (one full MF) time slot 16 contains three or more zeros over 16 consecutive frames (one full MF) time slot 16 contains at least a single one bit 6 in time slot 16 of frame 0 set to zero for two consecutive MF more than two zeros in two frames (512 bits) bit 3 of non-align frame set to zero for three consecutive occasions in 255-bit times, at least 32 ones are received ITU SPEC. G.732 4.2 G.732 5.2 O.162 2.1.5 O.162 1.6.1.2 O.162 2.1.4 G.775 / G.962
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SR2: STATUS REGISTER 2 (Address = 07 Hex) (MSB) RMF RAF TMF SEC SYMBOL RMF RAF TMF SEC TAF LOTC RCMF TSLIP POSITION SR2.7 SR2.6 SR2.5 SR2.4 SR2.3 SR2.2 SR2.1 SR2.0
TAF
LOTC
RCMF
(LSB) TSLIP
NAME AND DESCRIPTION Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available. Receive Align Frame. Set every 250ns at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Transmit Multiframe. Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. One Second Timer. Set on increments of one second based on RCLK. If CCR2.7=1, then this bit will be set every 62.5ms instead of once a second. Transmit Align Frame. Set every 250ns at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 3. ns). Will force the LOTC pin high if enabled via TCR2.0. Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every 2ms on an arbitrary boundary if CRC4 is disabled. Transmit Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data.
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IMR1: INTERRUPT MASK REGISTER 1 (Address = 16 Hex) (MSB) RSA1 RDMA RSA0 RSLIP RUA1 RRA SYMBOL RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS POSITION IMR1.7 IMR1.6 IMR1.5 IMR1.4 IMR1.3 IMR1.2 IMR1.1 IMR1.0 NAME AND DESCRIPTION Receive Signaling All Ones/Signaling Change. 0 = interrupt masked 1 = interrupt enabled Receive Distant MF Alarm. 0 = interrupt masked 1 = interrupt enabled Receive Signaling All Zeros/Signaling Change. 0 = interrupt masked 1 = interrupt enabled Receive Elastic Store Slip Occurrence. 0 = interrupt masked 1 = interrupt enabled Receive Unframed All Ones. 0 = interrupt masked 1 = interrupt enabled Receive Remote Alarm. 0 = interrupt masked 1 = interrupt enabled Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Loss of Sync. 0 = interrupt masked 1 = interrupt enabled
RCL
(LSB) RLOS
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IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex) (MSB) RMF RAF TMF SEC TAF LOTC SYMBOL RMF RAF TMF SEC TAF LOTC RCMF TSLIP POSITION IMR2.7 IMR2.6 IMR2.5 IMR2.4 IMR2.3 IMR2.2 IMR2.1 IMR2.0
RCMF
(LSB) TSLIP
NAME AND DESCRIPTION Receive CAS Multiframe. 0 = interrupt masked 1 = interrupt enabled Receive Align Frame. 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled One Second Timer. 0 = interrupt masked 1 = interrupt enabled Transmit Align Frame. 0 = interrupt masked 1 = interrupt enabled Loss Of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Receive CRC4 Multiframe. 0 = interrupt masked 1 = interrupt enabled Transmit-Side Elastic Store Slip Occurrence. 0 = interrupt masked 1 = interrupt enabled
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7. ERROR COUNT REGISTERS
The DS21354/DS21554 have a set of four counters that record bipolar or code violations, errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of these four counters is automatically updated on either one-second boundaries (CCR2.7 = 0) or every 62.5ms (CCR2.7 = 1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain performance data from either the previous second or the previous 62.5ms. The user can use the interrupt from the one-second timer to determine when to read these registers. The user has a full second (or 62.5ms) to read the counters before the data is lost. All four counters will saturate at their respective maximum counts and they will not rollover. 7.1. BPV or Code Violation Counter Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6 = 0, then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 codewords are not counted as BPVs. If CCR2.6 = 1, then the VCR counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10** - 2 before the VCR would saturate. VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address = 00 Hex) VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address = 01 Hex) (MSB) (LSB) V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 SYMBOL V15 V0 POSITION VCR1.7 VCR2.0 NAME AND DESCRIPTION MSB of the 16-bit code violation count. LSB of the 16-bit code violation count.
VCR1 VCR2
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7.2. CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. CRCCR1: CRC4 COUNT REGISTER 1 (Address = 02 Hex) CRCCR2: CRC4 COUNT REGISTER 2 (Address = 03 Hex) (MSB)
(See Note) (See Note) (See Note) (See Note) (See Note) (See Note)
CRC7 SYMBOL CRC9 CRC0
CRC6
CRC5
CRC4
CRC3
CRC2
CRC9 CRC1
(LSB) CRC8 CRC0
CRCCR1 CRCCR2
POSITION CRCCR1.1 CRCCR2.0
NAME AND DESCRIPTION MSB of the 10-Bit CRC4 error count LSB of the 10-Bit CRC4 error count
Note: The upper six bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error counter.
7.3. E-Bit Counter E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 10-bit counter that records Far-End Block Errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. EBCR1: E-BIT COUNT REGISTER 1 (Address = 04 Hex) EBCR2: E-BIT COUNT REGISTER 2 (Address = 05 Hex) (MSB)
(See Note) (See Note) (See Note) (See Note) (See Note) (See Note)
EB7 SYMBOL EB9 EB0
EB6
EB5
EB4
EB3
EB2
EB9 EB1
(LSB) EB8 EB0
EBCR1 EBCR2
POSITION EBCR1.1 EBCR2.0
NAME AND DESCRIPTION MSB of the 10-Bit E-Bit Error Count LSB of the 10-Bit E-Bit Error Count
Note: The upper six bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
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7.4. FAS Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12-bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter is disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one second period is 4000, this counter cannot saturate. FASCR1: FAS ERROR COUNT REGISTER 1 (Address = 02 Hex) FASCR2: FAS ERROR COUNT REGISTER 2 (Address = 04 Hex) (MSB) FAS11 FAS10 FAS9 FAS8 FAS7 FAS6 (Note 1) FAS5 FAS4 FAS3 FAS2 FAS1 FAS0 (Note 2) SYMBOL FAS11 FAS0 POSITION FASCR1.7 FASCR2.2 NAME AND DESCRIPTION MSB of the 12-Bit FAS Error Count LSB of the 12-Bit FAS Error Count
(LSB) (Note 1) (Note 2)
FASCR1 FASCR2
Note 1: The lower two bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-Bit counter. Note 2: The lower two bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error counter.
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8. DS0 MONITORING FUNCTION
Each framer in the DS21354/DS21554 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits appears in the transmit DS0 monitor (TDS0M) register, and the DS0 channel pointed to by the RCM0 to RCM4 bits appears in the receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate E1 channel. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction need to be monitored, then the following values would be programmed into CCR5 and CCR6: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1
[Repeated here from Section 5 for convenience.]
RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
CCR4: COMMON CONTROL REGISTER 4 (Address = A8 Hex) (MSB) RLB SYMBOL RLB LLB LIAIS TCM4 TCM3 TCM2 TCM1 TCM0 LLB POSITION CCR4.7 CCR4.6 CCR4.5 CCR4.4 CCR4.3 CCR4.2 CCR4.1 CCR4.0 LIAIS TCM4 TCM3 TCM2 TCM1 (LSB) TCM0
NAME AND DESCRIPTION Remote Loopback. Local Loopback. Line Interface AIS Generation Enable. Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 8 for details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = A9 Hex) (MSB) B1 B2 B3 B4 B5 B6 SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 POSITION TDS0M.7 TDS0M.6 TDS0M.5 TDS0M.4 TDS0M.3 TDS0M.2 TDS0M.1 TDS0M.0
B7
(LSB) B8
NAME AND DESCRIPTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Transmit DS0 Channel Bit 6. Transmit DS0 Channel Bit 7. Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted).
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
[Repeated here from Section 5 for convenience]
(MSB) LIRST
RESALGN
TESALGN
RCM4
RCM3
RCM2
RCM1
(LSB) RCM0
SYMBOL LIRST RESALGN TESALGN RCM4 RCM3 RCM2 RCM1 RCM0
POSITION CCR5.7 CCR5.6 CCR5.5 CCR5.4 CCR5.3 CCR5.2 CCR5.1 CCR5.0
NAME AND DESCRIPTION Line Interface Reset. Receive Elastic Store Align. Transmit Elastic Store Align. Receive Channel Monitor Bit 4. MSB of a channel decode that determines in which receive channel the data will appear in the RDS0M register. See Section 8 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
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RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = AB Hex) (MSB) B1 B2 B3 B4 B5 B6 SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 POSITION RDS0M.7 RDS0M.6 RDS0M.5 RDS0M.4 RDS0M.3 RDS0M.2 RDS0M.1 RDS0M.0
B7
(LSB) B8
NAME AND DESCRIPTION Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 7. Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit received).
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9. SIGNALING OPERATION
The DS21354/DS21554 contain provisions for both processor-based (i.e., software-based) signaling bit access and for hardware-based access. Both the processor-based access and the hardware-based access can be used simultaneously if necessary. The processor-based signaling is covered in Section 9.1 and the hardware based signaling is covered in Section 9.2. When referring to signaling, the voice-channel numbering scheme is used. 9.1. Processor-Based Signaling The Channel-Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the receive stream and inserted into the transmit stream by the framer. Each of the 30 voice channels has four signaling bits (A/B/C/D) associated with it. The numbers in parentheses () are the voice channel associated with a particular signaling bit. The voice channel numbers have been assigned as described in the ITU documents. Please note that this is different than the channel numbering scheme (1 to 32) that is used in the rest of the data sheet. For example, voice channel 1 is associated with time slot 1 (Channel 2) and voice channel 30 is associated with time slot 31 (Channel 32). There is a set of 16 registers for the receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to TS16). The signaling registers are detailed below. RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address = 30 to 3F Hex) (MSB) (LSB) 0 0 0 0 X Y X X A(1) B(1) C(1) D(1) A(16) B(16) C(16) D(16) A(2) B(2) C(2) D(2) A(17) B(17) C(17) D(17) A(3) B(3) C(3) D(3) A(18) B(18) C(18) D(18) A(4) B(4) C(4) D(4) A(19) B(19) C(19) D(19) A(5) B(5) C(5) D(5) A(20) B(20) C(20) D(20) A(6) B(6) C(6) D(6) A(21) B(21) C(21) D(21) A(7) B(7) B(7) B(7) B(22) B(22) B(22) B(22) A(8) B(8) C(8) D(8) A(23) B(23) C(23) D(23) A(9) B(9) C(9) D(9) A(24) B(24) C(24) D(24) A(10) B(10) C(10) D(10) A(25) B(25) C(25) D(25) A(11) B(11) C(11) D(11) A(26) B(26) C(26) D(26) A(12) B(12) C(12) D(12) A(27) B(27) C(27) D(27) A(13) B(13) C(13) D(13) A(28) B(28) C(28) D(28) A(14) B(14) C(14) D(14) A(29) B(29) C(29) D(29) A(15) B(15) C(15) D(15) A(30) B(30) C(30) D(30) SYMBOL X Y A(1) D(30) POSITION RS1.0/1/3 RS1.2 RS2.7 1. RS16.0 NAME AND DESCRIPTION Spare Bits Remote Alarm Bit (integrated and reported in SR1.6) Signaling Bit A for Channel 1 Signaling Bit D for Channel 30
RS1 (30) RS2 (31) RS3 (32) RS3 (33) RS5 (34) RS6 (35) RS7 (36) RS8 (37) RS9 (38) RS10 (39) RS11 (3A) RS12 (3B) RS13 (3C) RS14 (3D) RS15 (3E) RS16 (3F)
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Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The user has a full 2ms to retrieve the signaling bits before the data is lost. The RS registers are updated under all conditions. Their validity should be qualified by checking for synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been loaded with data. The user has 2ms to retrieve the data before it is lost. The signaling data reported in RS1 to RS16 is also available at the RSIG and RSER pins. A change in the signaling bits from one multiframe to the next causes the RSA1 (SR1.7) and RSA0 (SR1.5) status bits to be set at the same time. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting either the IMR1.7 or IMR1.5 bit. Once a signaling change has been detected, the user has at least 1.75ms to read the data out of the RS1 to RS16 registers before the data is lost. TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address = 40 to 4F Hex) (MSB) (LSB) 0 0 0 0 X Y X X A(1) B(1) C(1) D(1) A(16) B(16) C(16) D(16) A(2) B(2) C(2) D(2) A(17) B(17) C(17) D(17) A(3) B(3) C(3) D(3) A(18) B(18) C(18) D(18) A(4) B(4) C(4) D(4) A(19) B(19) C(19) D(19) A(5) B(5) C(5) D(5) A(20) B(20) C(20) D(20) A(6) B(6) C(6) D(6) A(21) B(21) C(21) D(21) A(7) B(7) B(7) B(7) B(22) B(22) B(22) B(22) A(8) B(8) C(8) D(8) A(23) B(23) C(23) D(23) A(9) B(9) C(9) D(9) A(24) B(24) C(24) D(24) A(10) B(10) C(10) D(10) A(25) B(25) C(25) D(25) A(11) B(11) C(11) D(11) A(26) B(26) C(26) D(26) A(12) B(12) C(12) D(12) A(27) B(27) C(27) D(27) A(13) B(13) C(13) D(13) A(28) B(28) C(28) D(28) A(14) B(14) C(14) D(14) A(29) B(29) C(29) D(29) A(15) B(15) C(15) D(15) A(30) B(30) C(30) D(30) SYMBOL X Y A(1) D(30) POSITION TS1.0/1/3 TS1.2 TS2.7 1. TS16.0 NAME AND DESCRIPTION Spare Bits Remote Alarm Bit (integrated and reported in SR1.6) Signaling Bit A for Channel 1 Signaling Bit D for Channel 30
TS1 (40) TS2 (41) TS3 (42) TS4 (43) TS5 (44) TS6 (45) TS7 (46) TS8 (47) TS9 (48) TS10 (49) TS11 (4A) TS12 (4B) TS13 (4C) TS14 (4D) TS15 (4E) TS16 (4F)
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two time slots that will be inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the framer will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2.5) to know when to update the signaling bits. The bit will be set every 2ms, and the user has 2ms to update
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the TSRs before the old data is retransmitted. ITU specifications recommend that the ABCD signaling not be set to all zeros because they will emulate a CAS multiframe alignment word. The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble. The upper nibble must always be set to 0000 or else the terminal at the far end loses multiframe synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit should be set to one. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three remaining bits in TS1 are the spare bits. If they are not used, they should be set to one. In CCS signaling mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be informed when the signaling registers need to be loaded with data. The user has 2ms to load the data before the old data will be retransmitted. Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) to determine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from the TSER or TSIG pin (the corresponding bit in the TCBRs = 0). See Figure 18-15 for more details. 9.2.
9.2.1.
Hardware-Based Signaling
Receive Side
In the receive side of the hardware-based signaling, there are two operating modes for the signaling buffer--signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling bits from the receive data stream and buffering them over a four-multiframe buffer and outputting them in a serial PCM fashion on a channel-by-channel basis at the RSIG output. This mode is always enabled. In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) must be 2.048MHz/4.096MHz/8.192MHz. The ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (2ms) unless a freeze is in effect. See the timing diagrams in Section 18.1 for some examples. The other hardware-based signaling operating mode called signaling reinsertion can be invoked by setting the RSRE control bit high (CCR3.3 = 1). In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data is realigned at the RSER output according to this applied multiframe boundary. In this mode, the elastic store must be enabled and the backplane clock must be 2.048MHz/4.096MHz/8.192MHz. The signaling data in the two-multiframe buffer is frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit (CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization, carrier loss, or slip has occurred. The two-multiframe buffer provides an approximate one-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if RSRE = 1 via CCR3.3). When freezing is enabled (RFE = 1), the signaling data is held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data is held in the old state for an additional 3ms to 5ms before being allowed to be updated with new signaling data.
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9.2.2.
Transmit Side
Via the THSE control bit (CCR3.2), the DS21354/DS21554 can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The hardware signaling insertion capabilities of each framer are available whether the transmit-side elastic store is enabled or disabled. If the transmit-side elastic store is enabled, the backplane clock (TSYSCLK) must be 2.048MHz/4.096MHz/8.192MHz. When hardware signaling insertion is enabled on a framer (THSE = 1), then the user must enable the Transmit Channel Blocking Register Function Select (TCBFS) control bit (CCR3.6 = 1). This is needed so that the CAS multiframe alignment word, multiframe remote alarm, and spare bits can be added to time slot 16 in frame 0 of the multiframe. The TS1 register should be programmed with the proper information. If CCR3.6 = 1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER (or TSIG if CCR3.2 = 1) and a one implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS) registers. See definition below. TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1 (MSB) CH18 CH3 CH17 CH2 CH16 CH1 1* CH22 CH7 CH21 CH6 CH20 CH5 CH19 CH26 CH11 CH25 CH10 CH24 CH9 CH23 CH30 CH15 CH29 CH14 CH28 CH13 CH27 (LSB) 1* CH4 CH8 CH12
TCBR1(22) TCBR2(23) TCBR3(24) TCBR4(25)
*These bits should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits.
The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this application, the following bits and registers would be programmed as follows: CONTROL BITS THSE = 1 (CCR3.2) TCBFS = 1 (CCR3.6) T16S = 0 (TCR1.5) REGISTER VALUES TS1 = 0Bh (MF alignment word, remote alarm etc.) TCBR1 = 03h (source time slot 16, frame 1 data) TCBR2 = 01h (source voice Channel 5 signaling data from TS6) CBR3 = 04h (source voice Channel 10 signaling data from TS11) TCBR4 = 00h
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10.
PER-CHANNEL CODE GENERATION AND LOOPBACK
The DS21354/DS21554 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 10.1. The receive direction is from the E1 line to the backplane and is covered in Section 10.2. 10.1. Transmit-Side Code Generation In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. The first method covered in Section 10.1.1 was a feature contained in the original DS2153, while the second method covered in 10.1.2 is a new feature of the DS2154/DS21354/DS21554.
10.1.1. Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1 channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows the same 8-bit code to be placed into any of the 32 E1 channels. If this method is used, then the CCR3.5 control bit must be set to zero. Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per-Channel Loopback (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back. TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)
[Also used for Per-Channel Loopback]
(MSB) CH8 CH16 CH24 CH32 SYMBOL CH1 to CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1 CH9 CH17 CH25
TIR1 (26) TIR2 (27) TIR3 (28) TIR4 (29)
POSITION TIR1.0 to TIR4.7
NAME AND DESCRIPTION Transmit Idle Code Insertion Control Bits. 0 = do not insert the Idle Code in the TIDR into this channel 1 = insert the Idle Code in the TIDR into this channel
Note: If CCR3.5 = 1, then a zero in the TIRs implies that channel data is to be sourced from TSER, and a one implies that channel data is to be sourced from the output of the receive-side framer (i.e., Per-Channel Loopback; see Figure 2-1).
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TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex) (MSB) TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 SYMBOL TIDR7 TIDR0
10.1.2.
TIDR1
(LSB) TIDR0
POSITION TIDR.7 TIDR.0
NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last)
Per-Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8-bit code to be placed into each of the 32 E1 channels. TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address = 60 to 7F Hex)
(For brevity, only channel one is shown; see for other register address.)
(MSB) C7 SYMBOL C7 C0
C6
C5
C4
C3
C2
C1
(LSB) C0
TC1 (60)
POSITION TC1.7 TC1.0
NAME AND DESCRIPTION MSB of the Code (this bit is transmitted first) LSB of the Code (this bit is transmitted last)
TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER (Address = A0 to A3 Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 SYMBOL CH1 to CH32 POSITION TCC1.0 to TCC4.7
TCC1 (A0) TCC2 (A1) TCC3 (A2) TCC4 (A3)
NAME AND DESCRIPTION Transmit Channel Code Insertion Control Bits 0 = do not insert data from the TC register into the transmit data stream 1 = insert data from the TC register into the transmit data stream
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10.2. Receive-Side Code Generation On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code placed in the Receive Channel Registers (RC1 to RC32). This method allows a different 8-bit code to be placed into each of the 32 E1 channels. RC1 TO RC32: RECEIVE CHANNEL REGISTERS (Address = 80 to 9F Hex)
(For brevity, only channel one is shown. See Table 4-1 for other register address.)
(MSB) C7 SYMBOL C7 C0
C6
C5
C4
C3
C2
C1
(LSB) C0
RC1 (80)
POSITION RC1.7 RC1.0
NAME AND DESCRIPTION MSB of the Code (this bit is sent first to the backplane) LSB of the Code (this bit is sent last to the backplane)
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER (Address = A4 to A7 Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 SYMBOL CH1 to CH32 POSITION RCC1.0 to RCC4.7
RCC1 (A4) RCC2 (A5) RCC3 (A6) RCC4 (A7)
NAME AND DESCRIPTION Receive Channel Code Insertion Control Bits 0 = do not insert data from the RC1 register into the receive data stream 1 = insert data from the RC1 register into the receive data stream
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11.
CLOCK BLOCKING REGISTERS
The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. (The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to one, the RCHBLK and TCHBLK pin will be held high during the entire corresponding channel time. See the timing in Section 18 for an example. The TCBRs have alternate mode of use. Via the CCR3.6 bit, the user has the option to use the TCBRs to determine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from the TSER or TSIG pins (the corresponding bit in the TCBR = 0). See the timing in Section 18.2 for an example. RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS (Address = 2B to 2E Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RCBR1 (2B) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RCBR2 (2C) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RCBR3 (2D) CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 RCBR4 (2E) SYMBOL CH1 to CH32 POSITION RCBR1.0 to RCBR4.7 NAME AND DESCRIPTION Receive Channel Blocking Control Bits. 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS (Address = 22 to 25 Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TCBR1 (22) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TCBR2 (23) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TCBR3 (24) CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 TCBR4 (25) SYMBOL CH1 to CH32 POSITION TCBR1.0 to TCBR4.7 NAME AND DESCRIPTION Transmit Channel Blocking Control Bits. 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time
Note: If CCR3.6 = 1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER (or TSIG if CCR3.2 = 1), and a one implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS) registers. In this mode, the voice-channel numbering scheme (CH1 to CH30) is used. See the following definition.
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TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1 (MSB) CH18 CH3 CH17 CH2 CH16 CH1 1* CH22 CH7 CH21 CH6 CH20 CH5 CH19 CH26 CH11 CH25 CH10 CH24 CH9 CH23 CH30 CH15 CH29 CH14 CH28 CH13 CH27
(LSB) 1* CH4 CH8 CH12
TCBR1(22) TCBR2(23) TCBR3(24) TCBR4(25)
*These bits should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits.
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12.
ELASTIC STORES OPERATION
The DS21354/DS21554 contain dual two-frame (512 bits) elastic stores, one for the receive direction and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the E1 data stream to 1.544Mbps (or a multiple of 1.544Mbps), which is the T1 rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not frequency locked) backplane clock, which can be 1.544MHz or 2.048MHz/4.096MHz/8.192MHz. The backplane clock can burst at rates up to 8.192MHz. Both elastic stores contain full-controlled slip capability, which is necessary for this second purpose. The elastic stores can be forced to a known depth via the Elastic Store Reset bits (CCR6.0 and CCR6.1). Toggling these bits forces the read and write pointers into opposite frames. Both elastic stores within a framer are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to them. The transmit-side elastic store can be enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/8.192MHz backplane without regard to the backplane rate the other elastic store is interfacing. 12.1. Receive Side If the receive-side elastic store is enabled (RCR2.1 = 1), then the user must provide either a 1.544MHz (RCR2.2 = 0) or 2.048MHz/4.096MHz/8.192MHz (RCR2.2 = 1) clock at the RSYSCLK pin. The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR1.5 = 1) or having the RSYNC pin provide a pulse on frame/multiframe boundaries (RCR1.5 = 0). If the user wishes to obtain pulses at the frame boundary, then RCR1.6 must be set to zero. If the user wishes to have pulses occur at the multiframe boundary, then RCR1.6 must be set to one. The DS21354/DS21554 always indicate frame boundaries via the RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then either CAS (RCR1.7 = 0) or CRC4 (RCR1.7 = 1) multiframe boundaries will be indicated via the RMSYNC output. If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth channel of the received E1 data will be deleted, and an F-bit position (which will be forced to one) will be inserted. Hence, Channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received E1 data stream. Also, in 1.544MHz applications, the RCHBLK output will not be active in Channels 25 through 32 (or in other words, RCBR4 is not active). See Section 18.1 for timing details. If the 512-bit elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, then a full frame of data (256 bits) will be repeated at RSER, and the SR1.4 and RIR.3 bits will be set to one. If the buffer fills, then a full frame of data will be deleted, and the SR1.4 and RIR.4 bits will be set to one. 12.2. Transmit Side The operation of the transmit elastic store is very similar to the receive side. The transmit-side elastic store is enabled via CCR3.7. A 1.544MHz (CCR3.1 = 0) or 2.048MHz/4.096MHz/8.192MHz (CCR3.1 = 1) clock can be applied to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192MHz. The user must supply either an 8kHz frame-sync pulse or a multiframe-sync pulse to the TSSYNC input. See Section 18.2 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0 bit, and the direction of the slip is reported in the RIR.6 and RIR.7 bits.
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13.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS21354/DS21554 provide for access to both the Sa and the Si bits through three different methods. The first method is accomplished via a hardware scheme using the RLINK/RLCLK and TLINK/TLCLK pins (see Section 13.1). The second method involves using the internal RAF/RNAF and TAF/TNAF registers (see Section 13.2). The third method, which is covered in Section 13.3, involves an expanded version of the second method, and is one of the features added to the DS2154/354/554 from the original DS2153 definition. 13.1. Hardware Scheme On the receive side, all the received data is reported at the RLINK pin. Via RCR2, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will identify the Si bits. See Section 18.1 for detailed timing. On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see Section 13.2 for details) or from the external TLINK pin. Via TCR2, the framer can be programmed to source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits through the framer without them being altered, then the device should be set up to source all five Sa bits via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data flow diagram in Section 18.2 for examples. 13.2. Internal Register Scheme Based On Double Frame On the receive side, the RAF and RNAF registers always report the data as it received in the Additional and International bit locations. The RAF and RNAF registers are updated with the setting of the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers. It has 250ms to retrieve the data before it is lost. On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the TAF and TNAF registers. It has 250ms to update the data or else the old data will be retransmitted. Data in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) has automatic E-bit insertion enabled. Data in the Sa bit position is overwritten if any of the TCR2.3 to TCR2.7 bits are set to one (see Section 13.1 for details). Please see the register descriptions for TCR1 and TCR2 and Figure 18-15 for more details.
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RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex) (MSB) Si 0 0 1 1 0 SYMBOL Si 0 0 1 1 0 1 1 POSITION RAF.7 RAF.6 RAF.5 RAF.4 RAF.3 RAF.2 RAF.1 RAF.0 NAME AND DESCRIPTION International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit.
1
(LSB) 1
RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address = 1F Hex) (MSB) Si 1 A Sa4 Sa5 Sa6 SYMBOL Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 POSITION RNAF.7 RNAF.6 RNAF.5 RNAF.4 RNAF.3 RNAF.2 RNAF.1 RNAF.0 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8.
Sa7
(LSB) Sa8
TAF: TRANSMIT ALIGN FRAME REGISTER (Address = 20 Hex) (MSB) Si 0 0 1 1 0 SYMBOL Si 0 0 1 1 0 1 1 POSITION TAF.7 TAF.6 TAF.5 TAF.4 TAF.3 TAF.2 TAF.1 TAF.0 NAME AND DESCRIPTION International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit.
1
(LSB) 1
Note: The TAF register must be programmed with the 7-bit FAS word. The DS21354/DS21554 do not automatically set these bits.
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TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address = 21 Hex) (MSB) Si 1 A Sa4 Sa5 Sa6 Sa7 SYMBOL Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 POSITION TNAF.7 TNAF.6 TNAF.5 TNAF.4 TNAF.3 TNAF.2 TNAF.1 TNAF.0 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm (used to transmit the alarm). Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8.
(LSB) Sa8
Note: Bit 6 of the TNAF register must be programmed to one. The DS21354/DS21554 do not automatically set this bit. 13.3. Internal Register Scheme Based On CRC4 Multiframe On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4 Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first received. Please see the register descriptions below for more details. On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that via the Transmit Sa-Bit Control Register (TSaCR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 2 (SR2.5). The host can use the SR2.5 bit to know when to update these registers. It has 2ms to update the data or else the old data will be retransmitted. The MSB of each register is the first bit transmitted. Please see the register descriptions below and Figure 18-15 for more details.
REGISTER RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 TSiAF TSiNAF TRA TSa4 TSa5 TSa6 TSa7 TSa8 ADDRESS (HEX) 58 59 5A 5B 5C 5D 5E 5F 50 51 52 53 54 55 56 57 FUNCTION The eight Si bits in the align frame The eight Si bits in the non-align frame The eight reportings of the receive remote alarm (RA) The eight Sa4 reported in each CRC4 multiframe The eight Sa5 reported in each CRC4 multiframe The eight Sa6 reported in each CRC4 multiframe The eight Sa7 reported in each CRC4 multiframe The eight Sa8 reported in each CRC4 multiframe The eight Si bits to be inserted into the align frame The eight Si bits to be inserted into the non-align frame The eight settings of remote alarm (RA) The eight Sa4 settings in each CRC4 multiframe The eight Sa5 settings in each CRC4 multiframe The eight Sa6 settings in each CRC4 multiframe The eight Sa7 settings in each CRC4 multiframe The eight Sa8 settings in each CRC4 multiframe
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TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address = 1C Hex) (MSB) SiAF SiNAF RA Sa4 Sa5 Sa6 SYMBOL SiAF POSITION TSaCR.7
Sa7
(LSB) Sa8
SiNAF
TSaCR.6
RA Sa4 Sa5 Sa6 Sa7 Sa8
TSaCR.5 TSaCR.4 TSaCR.3 TSaCR.2 TSaCR.1 TSaCR.0
NAME AND DESCRIPTION International Bit in Align Frame Insertion Control Bit. 0 = do not insert data from the TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream International Bit in Non-Align Frame Insertion Control Bit. 0 = do not insert data from the TSiNAF register into the transmit data stream 1 = insert data from the TSiNAF register into the transmit data stream Remote Alarm Insertion Control Bit. 0 = do not insert data from the TRA register into the transmit data stream 1 = insert data from the TRA register into the transmit data stream Additional Bit 4 Insertion Control Bit. 0 = do not insert data from the TSa4 register into the transmit data stream 1 = insert data from the TSa4 register into the transmit data stream Additional Bit 5 Insertion Control Bit. 0 = do not insert data from the TSa5 register into the transmit data stream 1 = insert data from the TSa5 register into the transmit data stream Additional Bit 6 Insertion Control Bit. 0 = do not insert data from the TSa6 register into the transmit data stream 1 = insert data from the TSa6 register into the transmit data stream Additional Bit 7 Insertion Control Bit. 0 = do not insert data from the TSa7 register into the transmit data stream 1 = insert data from the TSa7 register into the transmit data stream Additional Bit 8 Insertion Control Bit. 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream
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14.
HDLC CONTROLLER FOR THE Sa BITS OR DS0
The DS21354/DS21554 can extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any multiple of DS0 or sub-DS0 channels. The SCT contains a complete HDLC controller (see Section 14). 14.1. General Overview The DS21354/DS21554 contain a complete HDLC controller with 64-byte buffers in both the transmit and receive directions The HDLC controller performs all the necessary overhead for generating and receiving an HDLC formatted message. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the HDLC data stream. There are 11 registers that the host uses to operate and control the operation of the HDLC controller. A brief description of the registers is shown in Table 14-1. Table 14-1. HDLC Controller Register List NAME HDLC Control Register (HCR) HDLC Status Register (HSR) HIMR Interrupt Mask Register (HIMR) Receive HDLC Information register (RHIR) Receive HDLC FIFO Register (RHFR) Receive HDLC DS0 Control Register 1 (RDC1) Receive HDLC DS0 Control Register 2 (RDC2) Transmit HDLC Information register (THIR) Transmit HDLC FIFO Register (THFR) Transmit HDLC DS0 Control Register 1 (TDC1) Transmit HDLC DS0 Control Register 2 (TDC2) FUNCTION general control over the HDLC controller key status information for both transmit and receive directions allows/stops status bits to/from causing an interrupt status information on receive HDLC controller access to 64-byte HDLC FIFO in receive direction controls the HDLC function when used on DS0 channels controls the HDLC function when used on DS0 channels status information on transmit HDLC controller access to 64-byte HDLC FIFO in transmit direction controls the HDLC function when used on DS0 channels controls the HDLC function when used on DS0 channels
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14.2. HDLC Status Registers Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of the bits in these three status registers are latched and some are real time bits that are not latched. Section 14.4 contains register descriptions that list which bits are latched and which are not. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other status registers in the framer, the user will always proceed a read of any of the three registers with a write. The byte written to the register will inform the framer which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with current value and it will be cleared. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically ANDed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write (for polled driven access) or write-read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21354/DS21554 with higher-order software languages. Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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14.3. Basic Operation Details As a basic guideline for interpreting and sending HDLC messages, the following sequences can be applied:
14.3.1. Example: Receive an HDLC Message
1. 2. 3. 4.
Enable RPS interrupts Wait for interrupt to occur Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt Read RHIR to obtain REMPTY status a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO a1. if CBYTE = 0 then skip to step 5 a2. if CBYTE = 1 then skip to step 7 b. If REMPTY = 1, then skip to step 6 5. Repeat step 4 6. Wait for interrupt, skip to step 4 7. If POK = 0, then discard whole packet, if POK = 1, accept the packet a. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
14.3.2. Example: Transmit an HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register 2. Enable either the THALF or TNF interrupt 3. Read THIR to obtain TFULL status a. If TFULL = 0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be written, in this case set TEOM = 1 before writing the byte and then skip to step 6) b. If TFULL = 1, then skip to step 5 4. Repeat step 3 5. Wait for interrupt, skip to step 3 6. Disable THALF or TNF interrupt and enable TMEND interrupt 7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
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14.4. HDLC Register Description HCR: HDLC CONTROL REGISTER (Address = B0 Hex) (MSB) -- RHR TFS THR TABT SYMBOL -- RHR TFS THR TABT POSITION HCR.7 HCR.6 HCR.5 HCR.4 HCR.3 (LSB) TCRCD
TEOM
TZSD
TEOM
HCR.2
TZSD TCRCD
HCR.1 HCR.0
NAME AND DESCRIPTION Not Assigned. Should be set to zero when written. Receive HDLC Reset. A 0-to-1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. Transmit Flag/Idle Select. 0 = 7Eh 1 = FFh Transmit HDLC Reset. A 0-to-1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. Transmit Abort. A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Transmit End of Message. Should be set to a one just before the last data byte of a HDLC packet is written into the transmit FIFO at THFR. This bit will be cleared by the HDLC controller when the last byte has been transmitted. Transmit Zero Stuffer Defeat. Overrides internal enable. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Transmit CRC Defeat. 0 = enable CRC generation (normal operation) 1 = disable CRC generation
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HSR: HDLC STATUS REGISTER (Address = B1 Hex) (MSB) FRCL RPE RPS RHALF RNE SYMBOL FRCL POSITION HSR.7
THALF
TNF
(LSB) TMEND
RPE
HSR.6
RPS RHALF RNE THALF TNF TMEND
HSR.5 HSR.4 HSR.3 HSR.2 HSR.1 HSR.0
NAME AND DESCRIPTION Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1) consecutive zeros have been detected at RPOSI and RNEGI. Receive Packet End. Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. The setting of this bit prompts the user to read the RHIR register for details. Receive Packet Start. Set when the HDLC controller detects an opening byte. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Half Full. Set when the receive 64-byte FIFO fills beyond the halfway point. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Not Empty. Set when the receive 64-byte FIFO has at least one byte available for a read. The setting of this bit prompts the user to read the RHIR register for details. Transmit FIFO Half Empty. Set when the transmit 64-byte FIFO empties beyond the halfway point. The setting of this bit prompts the user to read the THIR register for details. Transmit FIFO Not Full. Set when the transmit 64-byte FIFO has at least one byte available. The setting of this bit prompts the user to read the THIR register for details. Transmit Message End. Set when the transmit HDLC controller has finished sending a message. The setting of this bit prompts the user to read the THIR register for details.
Note: The RPE, RPS, and TMEND bits are latched and are cleared when read.
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HIMR: HDLC INTERRUPT MASK REGISTER (Address = B2 Hex) (MSB) FRCL RPE RPS RHALF RNE THALF SYMBOL FRCL RPE RPS RHALF RNE THALF TNF TMEND POSITION HIMR.7 HIMR.6 HIMR.5 HIMR.4 HIMR.3 HIMR.2 HIMR.1 HIMR.0 NAME AND DESCRIPTION Framer Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Packet End. 0 = interrupt masked 1 = interrupt enabled Receive Packet Start. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Half Full. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Not Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Half Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Not Full. 0 = interrupt masked 1 = interrupt enabled Transmit Message End. 0 = interrupt masked 1 = interrupt enabled
TNF
(LSB) TMEND
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RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = B3 Hex) (MSB) RABT RCRCE ROVR RVM REMPTY POK CBYTE SYMBOL RABT RCRCE ROVR RVM REMPTY POK CBYTE OBYTE POSITION RHIR.7 RHIR.6 RHIR.5 RHIR.4 RHIR.3 RHIR.2 RHIR.1 RHIR.0
(LSB) OBYTE
NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a row. CRC Error. Set when the CRC checksum is in error. Overrun. Set when the HDLC controller has attempted to write a byte into an already full receive FIFO. Valid Message. Set when the HDLC controller has detected and checked a complete HDLC packet. Empty. A real-time bit that is set high when the receive FIFO is empty. Packet OK. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the CRC was correct). Closing Byte. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a message (whether the message was valid or not). Opening Byte. Set when the byte available for reading in the receive FIFO at RHFR is the first byte of a message.
Note: The RABT, RCRCE, ROVR, and RVM bits are latched and are cleared when read. RHFR: RECEIVE HDLC FIFO REGISTER (Address = B4 Hex) (MSB) HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 SYMBOL HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 POSITION RHFR.7 RHFR.6 RHFR.5 RHFR.4 RHFR.3 RHFR.2 RHFR.1 RHFR.0
HDLC1
(LSB) HDLC0
NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte.
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THIR: TRANSMIT HDLC INFORMATION REGISTER (Address = B6 Hex) (MSB) -- -- -- -- -- TEMPTY TFULL SYMBOL -- -- -- -- -- TEMPTY TFULL TUDR POSITION THIR.7 THIR.6 THIR.5 THIR.4 THIR.3 THIR.2 THIR.1 THIR.0
(LSB) TUDR
NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Transmit FIFO Empty. A real-time bit that is set high when the FIFO is empty. Transmit FIFO Full. A real-time bit that is set high when the FIFO is full. Transmit FIFO Underrun. Set when the transmit FIFO empties out without the TEOM control bit being set. An abort is automatically sent.
Note: The TUDR bit is latched and is cleared when read.
THFR: TRANSMIT HDLC FIFO REGISTER (Address = B7 Hex) (MSB) HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 SYMBOL HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 POSITION THFR.7 THFR.6 THFR.5 THFR.4 THFR.3 THFR.2 THFR.1 THFR.0
HDLC1
(LSB) HDLC0
NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte.
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RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address = B8 Hex) (MSB) RHS RSaDS RDS0M RD4 RD3 RD2 RD1 SYMBOL RHS POSITION RDC1.7
(LSB) RD0
RSaDS
RDC1.6
RDS0M RD4 RD3 RD2 RD1 RD0
RDC1.5 RDC1.4 RDC1.3 RDC1.2 RDC1.1 RDC1.0
NAME AND DESCRIPTION Receive HDLC source 0 = Sa bits defined by RCR2.3 to RCR2.7. 1 = Sa bits or DS0 channels defined by RDC1 (see bits defined below). Receive Sa Bit/DS0 Select. 0 = route Sa bits to the HDLC controller. RD0 to RD4 defines which Sa bits are to be routed. RD4 corresponds to Sa4, RD3 to Sa5, RD2 to Sa6, RD1 to Sa7 and RD0 to Sa8. 1 = route DS0 channels into the HDLC controller. RDC1.5 is used to determine how the DS0 channels are selected. DS0 Selection Mode. 0 = utilize the RD0 to RD4 bits to select which single DS0 channel to use. 1 = utilize the RCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select.
RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address = B9 Hex) (MSB) RDB8 RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 SYMBOL RDB8 RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 RDB1 POSITION RDC2.7 RDC2.6 RDC2.5 RDC2.4 RDC2.3 RDC2.2 RDC2.1 RDC2.0
(LSB) RDB1
NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used.
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TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = BA Hex) (MSB) THE TSaDS TDS0M TD4 TD3 TD2 TD1 SYMBOL POSITION
(LSB) TD0
THE
TDC1.7
TSaDS
TDC1.6
TDS0M TD4 TD3 TD2 TD1 TD0
TDC1.5 TDC1.4 TDC1.3 TDC1.2 TDC1.1 TDC1.0
NAME AND DESCRIPTION Transmit HDLC Enable. 0 = disable HDLC controller (no data inserted by HDLC controller into the transmit data stream) 1 = enable HDLC controller to allow insertion of HDLC data into either the Sa position or multiple DS0 channels as defined by TDC1 (see bit definitions below). Transmit Sa Bit / DS0 Select. This bit is ignored if TDC1.7 is set to zero. 0 = route Sa bits from the HDLC controller. TD0 to TD4 defines which Sa bits are to be routed. TD4 corresponds to Sa4, TD3 to Sa5, TD2 to Sa6, TD1 to Sa7 and TD0 to Sa8. 1 = route DS0 channels from the HDLC controller. TDC1.5 is used to determine how the DS0 channels are selected. DS0 Selection Mode. 0 = utilize the TD0 to TD4 bits to select which single DS0 channel to use. 1 = utilize the TCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select.
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = BB Hex) (MSB) TDB8 TDB7 TDB6 TDB5 TDB4 TDB3 TDB2 SYMBOL TDB8 TDB7 TDB6 TDB5 TDB4 TDB3 TDB2 TDB1 POSITION TDC2.7 TDC2.6 TDC2.5 TDC2.4 TDC2.3 TDC2.2 TDC2.1 TDC2.0
(LSB) TDB1
NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used.
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15.
LINE INTERFACE FUNCTIONS
The line interface function in the DS21354/DS21554 contains three sections: (1) the receiver, which handles clock and data recovery; (2) the transmitter, which waveshapes and drives the E1 line; and (3) the jitter attenuator. Each of these three sections is controlled by The Line Interface Control Register (LICR) contrlls each of these three sections. LICR: LINE INTERFACE CONTROL REGISTER (Address = 18 Hex) (MSB) L2 L1 L0 EGL JAS JABDS SYMBOL L2 L1 L0 EGL JAS JABDS DJA TPD POSITION LICR.7 LICR.6 LICR.5 LICR.4 LICR.3 LICR.2 LICR.1 LICR.0 (LSB) TPD
DJA
NAME AND DESCRIPTION Line Build-Out Select Bit 2. Sets the transmitter build out (see Table 15-1 and Table 15-2). Line Build-Out Select Bit 1. Sets the transmitter build out (see Table 15-1 and Table 15-2). Line Build-Out Select Bit 0. Sets the transmitter build out (see Table 15-1 and Table 15-2). Receive Equalizer Gain Limit. 0 = -12dB 1 = -43dB Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Jitter Attenuator Buffer Depth Select. 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) Disable Jitter Attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled Transmit Power Down. 0 = normal transmitter operation 1 = powers down the transmitter and tri-states the TTIP and TRING pins
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15.1. Receive Clock and Data Recovery The DS21354/DS21554 contain a digital clock recovery system. See Figure 2-1 and Figure 15-1 for more details. The device couples to the receive-E1-shielded twisted pair or coax via a 1:1 transformer. See Table 15-3 for transformer details. The 2.048MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16-times oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding jitter tolerance (Figure 15-3). Normally, the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a receive carrier loss (RCL) condition occurs, and the RCLKO is sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKO output can exhibit slightly shorter high cycles of the clock, which is due to the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the Receive AC Timing Characteristics for more details. 15.2. Transmit Waveshaping and Line Driving The DS21354/DS21554 use a set of laser-trimmed delay lines along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications (see Figure 15-5). The user selects which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR). The DS21354/DS21554 can set up in a number of various configurations depending on the application. See tables below and Figure 15-5. Table 15-1. Line Build-Out Select in LICR for the DS21554
L2 0 0 0 0 1 1 1 L1 0 0 1 1 0 1 0 L0 0 1 0 1 0 0 0 APPLICATION 75W normal 120W normal 75W with protection resistors 120W with protection resistors 75W with high return loss 75W with high return loss 120W with high return loss TRANSFORMER 1:1.15 step-up 1:1.15 step-up 1:1.15 step-up 1:1.15 step-up 1:1.15 step-up 1:1.36 step-up 1:1.36 step-up RETURN LOSS (dB)* N.M. N.M. N.M. N.M. 21 21 21 RT (W)** 0 0 8.2 8.2 27 18 27
* N.M. = Not Meaningful (return loss value too low for significance). ** Refer to Application Note 324 for details on E1 line interface design.
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Table 15-2. Line Build-Out Select in LICR for the DS21354
L2 0 0 0 0 1 1 L1 0 0 1 1 0 0 L0 0 1 0 1 0 1 APPLICATION 75W normal 120W normal 75W with protection resistors 120W with protection resistors 75W with high return loss 120W with high return loss TRANSFORMER 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up RETURN LOSS (dB)* N.M. N.M. N.M. N.M. 21 21 RT (W)** 0 0 2.5 2.5 6.2 11.6
* N.M. = Not Meaningful (return loss value too low for significance). ** Refer to Application Note 324 for details on E1 line interface design.
Due to the nature of the design of the transmitter in the DS21354/DS21554, very little jitter (less than 0.005 UIP-P broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveform created is independent of the duty cycle of TCLK. The transmitter in the device couples to the E1transmit-shielded twisted pair or coax via a 1:1.15 or 1:1.36 step-up transformer as shown in Figure 15-1. For the devices to create the proper waveforms, the transformer used must meet the specifications listed in Table 15-3. The line driver in the device contains a current limiter that prevents more than 50mA (RMS) from being sourced in a 1W load. Table 15-3. Transformer Specifications
SPECIFICATION Turns Ratio for DS21354 Turns Ratio for DS21554 Primary Inductance Leakage Inductance Intertwining Capacitance DC Resistance RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) 3% 1:1 (receive) and 1:1.15 or 1:1.36 (transmit) 3% 600mH minimum 1.0mH maximum 40pF maximum 1.2W maximum
15.3. Jitter Attenuator The DS21354/DS21554 contain an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in Figure 15-4. The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. For the jitter attenuator to properly operate, a 2.048MHz clock (50ppm) must be applied at the MCLK pin, or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a crystal is applied across the MCLK and XTALD pins, then the maximum effective series resistance should be 30W, and capacitors should be placed from each leg of the crystal to ground as shown in Figure 15-2. On-board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLKI pin to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIP-P (buffer depth is 128 bits) or 28 UIP-P (buffer depth is 32 bits), then the DS21354/DS21554 divide the internal nominal 32.768MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
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Figure 15-1. Basic External Analog Connections
0.47 (nonpolarized) Rt E1 Transmit Line Rt N:1 (See Note 1) DS21354/DS21554 DVDD TTIP TRING DVSS RVDD RVSS 1:1 E1 Receive Line Rr 0.1mF Rr RTIP RRING MCLK 2.048MHz TVDD TVSS 0.1
VDD
0.01
0.1
0.1 + 10
NOTE 1: ALL CAPACITORS VALUES ARE IN mF. NOTE 2: 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION. NOTE 3: SEE TABLE 15-3 FOR TRANSFORMER SELECTION.
Figure 15-2. Optional Crystal Connection
XTALD DS21354/ DS21554 MCLK C1 C2
2.048MHz
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Figure 15-3. Jitter Tolerance
1K DS21354/ DS21554 Tolerance
UNIT INTERVALS (UIpp)
100
40
10
1.5
1
Minimum Tolerance Level as per ITU G.823 1 10
20
0.2
0.1
100 1K FREQUENCY (Hz)
2.4K
10K
18K
100K
Figure 15-4. Jitter Attenuation
0dB
JITTER ATTENUATION (dB)
ITU G.7XX Prohibited Area
n io at nu tte rA te Jit
-20dB
ETS 300 011 & TBR12 Prohibited Area
e rv Cu
-40dB
-60dB 1 10
40
100 1K FREQUENCY (Hz)
10K
100K
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Figure 15-5. Transmit Waveform Template
1.2 1.1 1.0
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 269ns
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
-250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns
SCALED AMPLITUDE
G.703 Template
TIME (ns)
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15.4. Protected Interfaces In certain applications, such as connecting to the PSTN, it is required that the network interface be protected from and resistant to certain electrical conditions. These conditions are divided into two categories, surge and power line cross. A typical cause of surge is lightening strike. Power-line cross refers to accidental contact with high-voltage power wiring. For protection against surges, additional components and PC board layout considerations are required to reroute and dissipate this energy. In a surge event, the network interface must not be damaged and continue to work after the event. In the event of a power line contact, components such as fuses or PTCs that can "open" the circuit are required to prevent the possibility of a fire caused by overheating the transformer. The circuit examples in this data sheet are for "Secondary Over Voltage Protection" schemes for the line terminating equipment. Primary protection is typically provided by the network service provide and is external to the equipment. Figure 15-6 shows an example circuit for the 5V device and Figure 15-7 is an example for the 3.3V device. In both examples, fuses are used to provide protection against power-line cross. Surge protection is provided by 470W input resistors on the receive pair, a transient suppresser, and a diode bridge on the transmit pair. Resistors R1 to R4 provide surge protection for the fuse. Careful selection of the transformer allows the use of a fuse that requires no additional surge protection such as the circuit shown in Figure 15-7. The circuit shown in Figure 15-7 is required for 3.3V operation since additional resistance in the transmit pair cannot be tolerated. For more information on line interface design, consult the E1 Line Interface Design Criteria and Secondary Overvoltage Protection application notes available on our website at www.maxim-ic.com/appnoteindex.
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Figure 15-6. Protected Interface Example for the DS21554
+5V
D1 Fuse
R1 R2
N:1
S
D2
DS21554
TTIP
+5.0V 0.01
Rt Rt C2
C1
D4
Transmit Line
Fuse
DVDD DVSS RVDD RVSS
0.1
+
TRING
68
X1
D3
0.1
Fuse
R3 R4
1:1
470
RTIP
Receive Line
Fuse
TVDD TVSS MCLK
470
RRING
0.1
+
10
X2 Rterm Rterm
0.1
2.048MHz
NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION. NOTE 3: THE 68mF CAPACITOR IS REQUIRED TO MAINTAIN VDD DURING A TRANSIENT EVENT. COMPONENT D1 TO D4 C1 C2 S FUSE RT RTERM R1 TO R4 X1 X2 FUNCTION SCHOTTKY DIODE, INTERNATIONAL RECTIFIER 11DQ04 0.1mF CERAMIC CAPACITOR IN PARALLEL WITH 10mF TANTALUM CAPACITOR 0.47mF, NONPOLARIZED CERAMIC CONSTRUCTION SEMTECH LC01-6, 6V LOW CAPACITANCE TVS FOR MORE INFORMATION ON THE SELECTION OF THESE COMPONENTS, REFER TO THE SEPARATE APPLICATION NOTES ON SECONDARY OVERVOLTAGE PROTECTION AND T1/E1 NETWORK INTERFACE DESIGN AVAILABLE ON OUR WEBSITE AT WWW.MAXIM-IC.COM/APPNOTEINDEX.
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Figure 15-7. Protected Interface Example for the DS21354
+3.3V
D1 Fuse
2:1
S
D2
DS21354
TTIP
+3.3V 0.01
Transmit Line
Fuse
C2
DVDD DVSS RVDD
C1 D3 D4
0.1
+
TRING
68
X1
0.1 RVSS
Fuse
1:1
470
RTIP
Receive Line
Fuse
TVDD TVSS MCLK
470
RRING
0.1
+
10
X2 37/60 37/60
0.1
2.048MHz
NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION. NOTE 3: THE 68mF CAPACITOR IS REQUIRED TO MAINTAIN VDD DURING A TRANSIENT EVENT. COMPONENT D1 TO D4 C1 C2 FUSE S X1, X2 FUNCTION SCHOTTKY DIODE, INTERNATIONAL RECTIFIER 11DQ04 0.1mF CERAMIC CAPACITOR IN PARALLEL WITH 10mF TANTALUM CAPACITOR 0.47mF, NONPOLARIZED CERAMIC CONSTRUCTION 1.25A SLO-BLO, LITTLEFUSE V2301.25 SEMTECH LC01-6, 6V LOW CAPACITANCE TVS TRANSPOWER PT314, LOW DCR
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15.5. Receive Monitor Mode When connecting to a monitor port, a large resistive loss is incurred due to the voltage divider between the E1 line termination resistors (Rt) and the monitor port isolation resistors (Rm), as shown in Figure 15-8. The receiver of the DS21354/DS21554 can provide gain to overcome the resistive loss of a monitor connection. This is typically a purely resistive loss/gain and should not be confused with the cable loss characteristics of an E1 transmission line. Via the TEST3 register as shown in Table 15-4, the receiver can be programmed to provide both 12dB and 30dB of gain. Figure 15-8. Typical Monitor Port Application
E1 LINE
PRIMARY E1 TERMINATING DEVICE Rm
X F M R
Rm
Rt DS21X54
MONITOR PORT JACK
SECONDARY E1 TERMINATING DEVICE
Table 15-4. Receive Monitor Mode Gain TEST3 (Address = AC hex) REGISTER VALUE 72 hex 70 hex GAIN (dB) 12 30
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16.
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS21354/DS21554 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Figure 16-1. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register
The DS21354/DS21554 are enhanced versions of the DS2152 and are backward pin compatible. The JTAG feature uses pins that had no function in the DS2152. When using the JTAG feature, be sure FMS (pin 76) is tied low, enabling the newly defined pins of the DS21354/DS21554. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in Section 3 for details.
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Figure 16-1. JTAG Functional Block Diagram
BOUNDARY SCAN REGISTER
IDENTIFICATION REGISTER
BYPASS REGISTER
INSTRUCTION REGISTER
SELECT
TEST ACCESS PORT
+V +V +V
OUTPUT ENABLE
10kW
10kW
10kW
MUX
JTDI
JTMS
JTCLK
JTRST
JTDO
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 16-2. Test-Logic-Reset Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test registers will remain idle. Select-DR-Scan All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state. Capture-DR Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. On the rising edge of JTCLK, the controller will go to the ShiftDR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH. Shift-DR The test data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. Exit1-DR While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-DR state. Pause-DR Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state. Exit2-DR A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the ShiftDR state. Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register.
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Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the Shift-IR state. Shift-IR In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers, remain at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift-IR state while moving data one stage thorough the instruction shift register. Exit1-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process. Pause-IR Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK. Exit2-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state. Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW, will put the controller in the Run-TestIdle state. With JTMS HIGH, the controller will enter the Select-DR-Scan state.
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Figure 16-2. TAP Controller State Diagram
Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 0 0 1 Exit2 DR 1 Update DR 1 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 1 1
1
0
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16.1. Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2IR state with JTMS HIGH will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS21354/DS21554 with their respective operational binary codes are shown in Table 16-1. Table 16-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001
SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the Shift-DR state. BYPASS When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device's normal operation. EXTEST This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register. CLAMP All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. HIGHZ All digital outputs of the device will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO. IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the
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rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a one in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See Table 16-2. Table 16-3 lists the device ID codes for the SCT devices. Table 16-2. ID Code Structure MSB Version Contact Factory 4 bits Table 16-3. Device ID Codes DEVICE DS21354 DS21554 DS21352 DS21552 16-BIT ID 0005h 0003h 0004h 0002h Device ID 16 bits JEDEC 00010100001 LSB 1 1
16.2. Test Registers IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the DS21354/554 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is n bits in length. See Table 16-4 for all the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions that provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See Table 16-3 and Table 16-4 for more information on bit usage.
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Table 16-4. Boundary Scan Control Bits
BIT 2 -- 1 -- -- 0 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 NAME RCHBLK JTMS 8MCLK JTCLK JTRST RCL JTDI N.C. N.C. JTDO BTS LIUC 8XCLK TEST N.C. RTIP RRING RVDD RVSS RVSS MCLK XTALD N.C. RVSS INT N/C N/C N/C TTIP TVSS TVDD TRING TCHBLK TLCLK TLINK TYPE O I O I I O I -- -- O I I O I -- I I BIT 62 61 60 59 58 57 56 55 54 PIN 36 -- 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 NAME CI TSYNC.cntl (Note 1) TSYNC TPOSI TNEGI TCLKI TCLKO TNEGO TPOSO DVDD DVSS TCLK TSER TSIG TESO TDATA TSYSCLK TSSYNC TCHCLK CO MUX BUS.cntl (Note 2) D0/AD0 D1/AD1 D2/AD2 D3/AD3 DVSS DVDD D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 TYPE I -- I/O I I I O O O BIT 29 28 27 26 25 24 23 22 21 -- -- 20 -- -- 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 PIN 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 -- 98 99 100 NAME A5 A6 ALE (AS)/A7 RD (DS) CS FMS WR (R/W) RLINK RLCLK DVSS DVDD RCLK DVDD DVSS RDATA RPOSI RNEGI RCLKI RCLKO RNEGO RPOSO RCHCLK RSIGF RSIG RSER RMSYNC RFSYNC RSYNC.cntl (Note 3) RSYNC RLOS/ LOTC RSYSCLK TYPE I I I I I I I O O -- -- O
-- -- -- --
72 71 70 69 68
-- --
53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 -- -- 38 37 36 35 34 33 32 31 30
-- --
I I I O I I I O O I -- I/O I/O I/O I/O
-- --
O I I I O O O O O O O O O -- I/O O I
-- -- -- -- -- -- --
67 -- 66
-- --
-- I O
-- --
O
-- -- -- -- -- -- --
65 64 63
-- -- --
O
-- --
I/O I/O I/O I/O I I I I I
-- --
O O O I
Note 1: Note 2: Note 3:
0 = TSYNC an input; 1 = TSYNC an output. 0 = D0-D7/AD0-AD7 are inputs; 1 = D0-D7/AD0-AD7 are outputs. 0 = RSYNC an input; 1 = RSYNC an output.
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17.
INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21354/DS21554 can be configured to allow data and signaling buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving board space and cost. The interleaved PCM bus option (IBO) supports two bus speeds. The 4.096 MHz bus speed allows two SCTs to share a common bus. The 8.192MHz bus speed allows four SCTs to share a common bus. See Figure 17-1 for an example of four devices sharing a common 8.192MHz PCM bus. Each SCT that shares a common bus must be configured through software and requires the use of one or two device pins. The elastic stores of each SCT must be enabled and configured for 2.048MHz operation. See Figure 17-1 and Table 17-1. For all bus configurations, one SCT will be configured as the master device and the remaining SCTs will be configured as slave devices. In the 4.096MHz bus configuration there is one master and one slave. In the 8.192MHz bus configuration there is one master and three slaves. Refer to the IBO register description for more detail. IBO: INTERLEAVE BUS OPERATION REGISTER (Address = B5 Hex) (MSB) -- -- -- -- IBOEN INTSEL MSEL0 SYMBOL -- -- -- -- IBOEN INTSEL MSEL0 MSEL1 POSITION IBO.6 IBO.6 IBO.5 IBO.4 IBO.3 IBO.2 IBO.1 IBO.0 NAME AND DESCRIPTION Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Interleave Bus Operation Enable 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Interleave Type Select 0 = Byte interleave. 1 = Frame interleave. Master Device Bus Select Bit 0. See Table 17-1. Master Device Bus Select Bit 1. See Table 17-1. (LSB) MSEL1
Table 17-1. IBO Master Device Select MSEL1 0 0 1 1 MSEL0 0 1 0 1 FUNCTION Slave device. Master device with 1 slave device (4.096MHz bus rate) Master device with 3 slave devices (8.192MHz bus rate) Reserved
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Figure 17-1. IBO Basic Configuration Using Four SCTs
CI
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER
CI
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER 8.192MHz System Clock In System 8KHz Frame Sync In PCM Signaling Out PCM Signaling In PCM Data In PCM Data Out
MASTER SCT
CO
SLAVE #2
CO
CI
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER
CI
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER
SLAVE #1
CO
SALVE #3
CO
17.1. Channel Interleave In channel interleave mode data is output to the PCM data-out bus one channel at a time from each of the connected SCTs until all channels of frame n from all each SCT has been place on the bus. This mode can be used even when the connected SCTs are operating asynchronous to each other. The elastic stores will manage slip conditions. See Figure 18-11 and Figure 18-5 for details. 17.2. Frame Interleave In frame-interleave mode, data is output to the PCM data-out bus one frame at a time from each of the connected SCTs. This mode is used only when all connected SCTs are synchronous. In this mode, slip conditions are not allowed. See Figure 18-2 and Figure 18-6 for details.
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18.
FUNCTIONAL TIMING DIAGRAMS
18.1. Receive Figure 18-1. Receive-Side Timing
FRAM E# RFSYNC RSYNC 1 RSYNC RLCLK RLINK
2 3 4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 1
NOTE 1: RSYNC IN FRAME MODE (RCR1.6 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (RCR1.6 = 1). NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE SA BITS. NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE SA BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM. NOTE 5: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled)
RCLK
CHANNEL 32
RSER RSYNC RFSYNC
CHANNEL 32
LSB
Si
1
A
CHANNEL 1 Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 2
CHANNEL 1 C D
Note 4
RSIG RCHCLK RCHBLK
1
A
B
CHANNEL 2 A B
RLCLK RLINK
2 Sa4 Sa5 Sa6 Sa7 Sa8
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 2: RLCLK IS PROGRAMMED TO MARK THE SA4 BIT IN RLINK. NOTE 3: SHOWN ISA RNAF FRAME BOUNDARY. NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
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Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
RSYSCLK
CHANNEL 23/31 CHANNEL 24/32
LSB
CHANNEL 1/2
RSER
1
LSB MSB
F
MSB
RSYNC2 RMSYNC RSYNC
3
RCHCLK RCHBLK
4
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS (MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ON1). NOTE 2: RSYNC IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 3: RSYNC IN THE INPUT MODE (RCR1.5 = 1). NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
RSYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB MSB
CHANNEL 1
RSER RSYNC1 RMSYNC
RSYNC
2
RSIG RCHCLK RCHBLK
3
A
CHANNEL 31 C B D
A
CHANNEL 32 C B D
CHANNEL 1
Note 4
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1). NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
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Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode
RSYNC R SER
1 FR1 CH32 FR1 CH32 FR0 CH1 FR0 CH1
FR1 CH1 FR1 CH1
FR1 CH1 FR1 CH1
FR2 CH1 FR2 CH1 FR3 CH1 FR3 CH1
FR0 CH2 FR0 CH2
FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2
FR1 CH2 FR1 CH2
FR2 CH2 FR2 CH2 FR3 CH2 FR3 CH2
R1 SIG R2 SER R2 SIG
FR2 CH32 FR3 CH32 FR0 CH1 FR2 CH32 FR3 CH32 FR0 CH1
BIT DETAIL SYSCLK RSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 1, CHANNEL 1
LSB
R SER R SIG
A B C
LSB MSB
FRAMER 3, CHANNEL 32
D
FRAMER 0, CHANNEL 1
A B C D
FRAMER 1, CHANNEL 1
A B C D
NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNC IS IN THE INPUT MODE (RCR1.5 = 0).
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Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode
RSYNC RE SR R IG S
1 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32
1
RE2 SR R IG S2
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
BIT DETAIL SYSCLK RSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 0, CHANNEL 2
LSB
RE SR R IG S
A B
LSB MSB
FRAMER 3, CHANNEL 32
C/A D/B
FRAMER 0, CHANNEL 1
A B C/A D/B
FRAMER 0, CHANNEL 2
A B C/A D/B
NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNC IS IN THE INPUT MODE (RCR1.5 = 0).
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18.2. Transmit Figure 18-7. Transmit-Side Timing
FRAME# TSYNC
1 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10
TSSYNC TSYNC TLCLK
2
3 3
TLINK
NOTE 1: TSYNC IN FRAME MODE (TCR1.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR1.1 = 1). NOTE 3: TLINK IS PROGRAMMED TO SOURCE JUST THE SA4 BIT. NOTE 4: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC4 MF BEGIN WITH THE TAF FRAME. NOTE 5: TLINK AND TLCLK ARE NOT SYNCHRONOUS WITH TSSYNC.
Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)
TCLK
CHANNEL 1 CHANNEL 2
LSB MSB
TSER TSYNC1 TSYNC2
LSB
Si
1
A Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 1
CHANNEL 2
A B C D
TSIG TCHCLK TCHBLK 3 TLCLK TLINK
4 4
D
DON'T CARE
DON'T CARE
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2. NOTE 4: TLINK IS PROGRAMMED TO SOURCE THE SA4 BIT. NOTE 5: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000). NOTE 6: SHOWN IS A TNAF FRAME BOUNDARY.
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Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
TSYSCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB F MSB
CHANNEL 1
TSER
1
TSSYNC TCHCLK TCHBLK
2
NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
TSYSCLK CHANNEL 31 TSER TSSYNC TSIG TCHCLK TCHBLK
1 LSB MSB
CHANNEL 32
LSB MSB
CHANNEL 1
CHANNEL 31
A B C D
CHANNEL 32
A B C D
CHANNEL 1
A
NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31.
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Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode
TSYNC TSER TSIG
1 FR1 CH32 FR1 CH32 FR0 CH1 FR0 CH1
FR1 CH1 FR1 CH1
FR1 CH1 FR1 CH1
FR2 CH1 FR2 CH1 FR3 CH1 FR3 CH1
FR0 CH2 FR0 CH2
FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2
FR1 CH2 FR1 CH2
FR2 CH2 FR2 CH2 FR3 CH2 FR3 CH2
1
TSER2 TSIG2
FR2 CH32 FR3 CH32 FR0 CH1 FR2 CH32 FR3 CH32 FR0 CH1
BIT DETAIL SYSCLK TSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 1, CHANNEL 1
LSB
TSER TSIG
A B
LSB MSB
FRAMER 3, CHANNEL 32
C/A D/B
FRAMER 0, CHANNEL 1
A B C/A D/B
FRAMER 1, CHANNEL 1
A B C/A D/B
NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
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Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode
TSYNC TSER TSIG
1 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32
1
TSER2 TSIG2
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
BIT DETAIL SYSCLK TSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 0, CHANNEL 2
LSB
TSER TSIG
A B
LSB MSB
FRAMER 3, CHANNEL 32
C/A D/B
FRAMER 0, CHANNEL 1
A B C/A D/B
FRAMER 0, CHANNEL 2
A B C/A D/B
NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
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Figure 18-13. G.802 Timing
TS # RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK
31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2
NOTE: RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH 25, AND BIT 1 OF TIME SLOT 26.
RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER RCHCLK / TCHCLK RCHBLK / TCHBLK
LSB MSB
CHANNEL 26
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Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart
Power Up
RLOS = 1
FAS Search FASSA = 1 RLOS = 1 FAS Sync Criteria Met FASSA = 0 Increment CRC4 Sync Counter; CRC4SA = 0 8ms Time Out CRC4 Multiframe Search (if enabled via CCR1.0) CRC4SA = 1 CAS Multiframe Search (if enabled via CCR1.3) CASSA = 1
Resync if RCR1.1 = 0
CRC4 Sync Criteria Met; CRC4SA = 0; Reset CRC4 Sync Counter
Sync Declared RLOS = 0
CAS Sync Criteria Met CASSA = 0
Set FASRC (RIR.1)
FAS Resync Criteria Met
Check for FAS Framing Error (depends on RCR1.2)
CRC4 Resync Criteria Met (RIR.2)
Check for >=915 Out of 1000 CRC4 Word Errors
If CRC4 is on (CCR1.0 = 1)
CAS Resync Criteria Met; Set CASRC (RIR.0)
Check for CAS MF Word Error
If CAS is on (CCR1.3 = 0)
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Figure 18-15. DS21354/DS21554 Transmit Data Flow
H LC D EG E N IN TN AF.0-4
0
TS ER & TD TA A
0 1
S Data Source a MX U (TD 1) C
1 TAF TN AF.5-7 1
DD S0 ata Source M X U (TD C1/2)
T 1 to T 3 C C2
TLINK
1
RE SR (note #1)
0
TAF/TN B AF it MX U
Per-C hannel C ode G eneration (TC C1/2/3/4)
0
0
1 Tim eslot 0 P ass-Through (TC 1.6) R 1 0 S B Insertion i it C ontrol (TC 1.3) R Receive Side CRC4 Error Detector 1 E it G -B eneration (TC 2.1) R 0 1 Sa Bit Insertion Control (TCR2.3 thru TCR2.7)
CCM R 4 ultifram e A lignm W ent ord G eneration (C R C .4)
0
TSiAF TSiNAF TRA TID R 0 1
T a to T a S4 S8
Auto R ote A em larm G eneration (C R C 2.4)
TIR Function S elect (C R C 3.5)
0 1 S Bit Insertion a C ontrol R egister (TS R aC ) TS1 to TS16 A IS G eneration
0 1 Idle C ode / C hannel Insertion C ontrol via TIR 1/2/3/4 TC R1/2/3/4 B 0 CR C 3.6
0 1 Transm S it ignaling AO ll nes (TC 1.2) R
1 S ignaling B it Insertion C ontrol C ode W ord G eneration 1 C RC4 E nable (CCR .4)
KEY:
= Register =D evice P in =S elector
TC 1.5 R
0
A IS G eneration
N TE O S: 1. TC should be tied to R LK and TSY C should be tied to R YN for LK C N FS C data to be properly sourced from R ER S. 2. A uto R ote Alarm if enabled w only overw bit 3 of tim em ill rite eslot 0 in the NA ot lign Fram if the alarm needs to be sent. es
0 1 Transm U it nfram A ed ll O nes (TC 1.4) or R A AIS (C R uto C 2.5) A o HDB MI r 3 C nve r o rte To W aveshaping and Line DriversTP S O,
C R .6 C1
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19.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground........................................................................-1.0V to +6.0V Operating Temperature Range for DS21354L/DS21554L............................................................0C to +70C Operating Temperature Range for DS21354LN/DS21554LN.....................................................-40C to +85C Storage Temperature Range.............................................................................................-55C to +125C Soldering Temperature.................................................................See IPC/JEDEC J-STD-020A Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDD = 3.3V 5%, TA = 0C to +70C; for DS21354L; VDD = 5.0V 5%, TA = 0C to +70C for DS21554L; VDD = 3.3V 5%, TA = -40C to +85C for DS21354LN; VDD = 5.0V 5%, TA = -40C to +85C for DS21554LN.)
PARAMETER Logic 1 Logic 0 Supply for DS21354 Supply for DS21554
SYMBOL VIH VIL VDD VDD
MIN 2.0 -0.3 3.135 4.75
TYP 3.3 5
MAX 5.5 +0.8 3.465 5.25
UNITS V V V V
NOTES 1 1
CAPACITANCE
(TA = +25C)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
MIN
TYP 5 7
MAX
UNITS pF pF
NOTES
DC CHARACTERISTICS
(VDD = 3.3V 5%, TA = 0C to +70C; for DS21354L; VDD = 5.0V 5%, TA = 0C to +70C for DS21554L; VDD = 3.3V 5%, TA = -40C to +85C for DS21354LN; VDD = 5.0V 5%, TA = -40C to +85C for DS21554LN.)
PARAMETER Supply Current at 5V Supply Current at 3.3V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V)
SYMBOL IDD IDD IIL ILO IOH IOL
MIN -1.0 -1.0 +4.0
TYP 75 75
MAX +1.0 1.0
UNITS mA mA mA mA mA mA
NOTES 2 2 3 4
Note 1: Applies to RVDD, TVDD, and DVDD. Note 2: TCLK = TCLKI = RCLKI = TSYSCLK = RSYSCLK = MCLK = 2.048MHz; outputs open circuited. Note 3: 0.0V < VIN < VDD. Note 4: Applied to INT when tri-stated.
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20.
AC TIMING PARAMETERS AND DIAGRAMS
20.1. Multiplexed Bus AC Characteristics AC CHARACTERISTICS--MULTIPLEXED PARALLEL PORT (MUX = 1)
(VDD = 3.3V 5%, TA = 0C to +70C; for DS21354L; VDD = 5.0V 5%, TA = 0C to +70C for DS21554L; VDD = 3.3V 5%, TA = -40C to +85C for DS21354LN; VDD = 5.0V 5%, TA = -40C to +85C for DS21554LN.) (See Figure 20-1 to Figure 20-3.)
PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Yimes R/W Hold Time R/W Setup Time before DS High CS Setup Time before DS, WR, or RD Active CS Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid to AS or ALE Fall Muxed Address Hold Time Delay time DS, WR, or RD to AS or ALE Rise Pulse Width AS or ALE High Delay time, AS or ALE to DS, WR, or RD Output Data Delay Time from DS or RD Data Setup Time
SYMBOL tCYC PWEL PWEH tR , tF tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW
MIN 200 100 100 10 50 20 0 10 0 15 10 20 30 10 20 50
TYP
MAX
20
UNITS ns ns ns ns ns ns ns
NOTES
50
ns ns ns ns ns ns ns ns ns ns
80
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Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1)
t CYC ALE t ASD WR
PWASH t ASED PWEH t CS t CH
t ASD PWEL
RD
CS t ASL AD0-AD7 t AHL t DDR t DHR
Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1)
t CYC ALE t ASD RD
PWASH t ASED PWEH t CS t CH
t ASD PWEL
WR
CS t ASL AD0-AD7 t AHL t DSW t DHW
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Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1)
PWASH AS t ASD DS PWEL t RWS R/W AD0-AD7
(READ)
t ASED t CYC
PWEH
t RWH t DDR
t ASL t AHL
t DHR t CH t DSW t DHW
t CS
CS AD0-AD7
(WRITE)
t ASL t AHL
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20.2. Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS--NONMULTIPLEXED PARALLEL PORT (MUX = 0)
(VDD = 3.3V 5%, TA = 0C to +70C; for DS21354L; VDD = 5.0V 5%, TA = 0C to +70C for DS21554L; VDD = 3.3V 5%, TA = -40C to +85C for DS21354LN; VDD = 5.0V 5%, TA = -40C to +85C for DS21554LN.) (See Figure 20-4 to Figure 20-7.)
PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active to Either RD, WR, or DS Active Delay Time from Either RD or DS Active to Data Valid Hold Time from Either RD, WR, or DS Inactive to CS Inactive Hold Time from CS Inactive to Data Bus Tri-State Wait Time from Either WR or DS Active to Latch Data Data Setup Time to Either WR or DS Inactive Data Hold Time from Either WR or DS Inactive Address Hold from Either WR or DS Inactive
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9
MIN 0 0
TYP
MAX
UNITS ns ns
NOTES
75 0 5 75 10 10 10 20
ns ns ns ns ns ns ns
Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0)
A0-A7 D0-D7 ADDRESS VALID DATA VALID 5ns MIN/20ns MAX
WR
t5
t1
CS
0ns MIN
0ns MIN
RD
t2
75ns MAX
t3
t4
0ns MIN
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Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0)
A0-A7 D0-D7 t7
RD
ADDRESS VALID
t8 10ns MIN
t1
CS
10ns MIN 0ns MIN t2 t6 75ns MIN
0ns MIN
WR
t4
0ns MIN
Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0)
A0-A7 D0-D7 ADDRESS VALID DATA VALID 5ns MIN/20ns MAX R/W t1
CS
t5
0ns MIN t2 t3 75ns MAX t4 0ns MIN
0ns MIN
DS
Figure 20-7. Motorola Bus Write AC Timing (BTS = 1/MUX = 0)
A0-A7 D0-D7 10ns MIN t1
CS
ADDRESS VALID
R/W 0ns MIN t2 t6 75ns MIN
t7 t8
10ns MIN
0ns MIN
DS
t4
0ns MIN
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
20.3. Receive-Side AC Characteristics AC CHARACTERISTICS--RECEIVE SIDE
(VDD = 3.3V 5%, TA = 0C to +70C; for DS21354L; VDD = 5.0V 5%, TA = 0C to +70C for DS21554L; VDD = 3.3V 5%, TA = -40C to +85C for DS21354LN; VDD = 5.0V 5%, TA = -40C to +85C for DS21554LN.) (See Figure 20-8 to Figure 20-10.)
PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width RCLKI Period RCLKI Pulse Width
RSYSCLK Period
RSYSCLK Pulse Width RSYNC Setup to RSYSCLK Falling RSYNC Pulse Width RPOSI/RNEGI Setup to RCLKI Falling RPOSI/RNEGI Hold From RCLKI Falling RSYSCLK/RCLKI Rise and Fall Times Delay RCLKO to RPOSO, RNEGO Valid Delay RCLK to RSER, RDATA, RSIG, RLINK Valid Delay RCLK to RCHCLK, RSYNC, RCHBLK, RFSYNC, RLCLK Delay RSYSCLK to RSER, RSIG Valid Delay RSYSCLK to RCHCLK, RCHBLK, RMSYNC, RSYNC, CO CI Setup to RSYSCLK Rising CI Pulse Width
SYMBOL tLP tLH tLL tLH tLL tCP tCH tCL tSP tSP tSP tSP tSH tSL tSU tPW tSU tHD tR , tF tDD tD1 tD2 tD3 tD4 tSC tWC
MIN 200 200 150 150 75 75 100 100 100 100 50 50 20 50 20 20
TYP 488 244 244 244 244 488
MAX
648 488 244 122
tSH -5
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES 1 1 2 2
3 4 5 6
25 50 50 50 50 50 20 50
Note 1: Jitter attenuator enabled in the receive path. Note 2: Jitter attenuator disabled or enabled in the transmit path. Note 3: RSYSCLK = 1.544MHz. Note 4: RSYSCLK = 2.048MHz. Note 5: RSYSCLK = 4.096MHz. Note 6: RSYSCLK = 8.192MHz.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 20-8. Receive-Side AC Timing
RCLK t D1 RSER / RDATA / RSIG t D2 RCHCLK t D2 RCHBLK t RFSYNC / RMSYNC t D2 1 RSYNC t D2 2 RLCLK t D1 RLINK
Sa4 to Sa8 Bit Position MSB of Channel 1
D2
Notes: 1. RSYNC is in the output mode (RCR1.5 = 0). 2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between RLCLK and RSYNC or RFSYNC is implied.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 20-9. Receive System Side AC Timing
t SL t SH
tR RSYSCLK t D3 RSER / RSIG tD4 RCHCLK
tF
tSP
MSB of Channel 1
tD4 RCHBLK t RMSYNC / CO t D4 1 RSYNC t SU 2 RSYNC t SC CI
Notes: 1. RSYNC is in the output mode (RCR1.5 = 0) 2. RSYNC is in the input mode (RCR1.5 = 1)
D4
t HD
t WC
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 20-10. Receive Line Interface AC Timing
tLL RCLKO tDD RPOSO, RNEGO tLH
tLP
tR RCLKI
tF tSU
tCL
tCH
tCP
RPOSI, RNEGI tHD
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20.4. Transmit AC Characteristics AC CHARACTERISTICS--TRANSMIT SIDE
(VDD = 3.3V 5%, TA = 0C to +70C; for DS21354L; VDD = 5.0V 5%, TA = 0C to +70C for DS21554L; VDD = 3.3V 5%, TA = -40C to +85C for DS21354LN; VDD = 5.0V 5%, TA = -40C to +85C for DS21554LN.) (See Figure 20-11 to Figure 20-13.)
PARAMETER TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width
TSYSCLK Period
TSYSCLK Pulse Width TSYNC or TSSYNC Setup to TCLK or TSYSCLK Falling TSYNC or TSSYNC Pulse Width TSER, TSIG, TDATA, TLINK, TPOSI, TNEGI Setup to TCLK, TSYSCLK, TCLKI Falling TSER, TSIG, TDATA, TLINK, TPOSI, TNEGI Hold from TCLK, TSYSCLK, TCLKI Falling TCLK, TCLKI, or TSYSCLK Rise and Fall Times Delay TCLKO to TPOSO, TNEGO Valid Delay TCLK to TESO Valid Delay TCLK to TCHBLK, TCHCLK, TSYNC, TLCLK Delay TSYSCLK to TCHCLK, TCHBLK, CO CI Setup to TSYSCLK Rising CI Pulse Width
Note 1: TSYSCLK = 1.544MHz. Note 2: TSYSCLK = 2.048MHz. Note 3: TSYSCLK = 4.096MHz. Note 4: TSYSCLK = 8.192MHz.
SYMBOL tCP tCH tCL tLP tLH tLL tSP tSP tSP tSP tSH tSL tSU tPW tSU tHD tR , tF tDD tD1 tD2 tD3 tSC tWC
MIN 75 75
TYP 488
MAX
488 75 75 100 100 100 100 50 50 20 50 20 20 25 50 50 50 75 20 50 648 448 244 122 tCH -5 or tSH -5
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES
1 2 3 4
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 20-11. Transmit-Side AC Timing
t CP tR TCLK t D1 TESO TSER / TSIG / TDATA t D2 TCHCLK TCHBLK t D2 TSYNC1 t SU TSYNC2 5 TLCLK t D2 t HD TLINK t SU
Notes: 1. TSYNC is in the output mode (TCR1.0 = 1). 2. TSYNC is in the input mode (TCR1.0 = 0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between TLCLK/TLINK and TSYNC is implied.
tF
t CL
t CH
t SU t HD
t D2
t HD
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 20-12. Transmit System Side AC Timing
t SP tR TSYSCLK t SU TSER t D3 TCHCLK / CO t D3 TCHBLK t SU TSSYNC t SC CI
Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
tF
t SL
t SH
t HD
t HD t WC
Figure 20-13. Transmit Line Interface Side AC Timing
TCLKO
TPOSO, TNEGO t DD tR TCLKI t SU TPOSI, TNEGI t HD tF t LL t LP t LH
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
21.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2004 Maxim Integrated Products * Printed USA
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